A Low-Voltage High-Precision Time-Domain Winner-Take-All Circuit

Lee

IEEE Trans. Circuits Syst. II

et al. 2022

In-Memory Computing (IMC) has been widely studied to mitigate data transfer bottlenecks in von Neumann architectures. Recently proposed IMC circuit topologies dramatically reduce data transfer requirements by performing various operations such as Multiply-Accumulate (MAC) inside the memory. In this paper, we present an SRAM macro designed for accelerating Memory-Augmented Neural Network (MANN). We first propose algorithmic optimizations for a few-shot learning algorithm employing MANN for efficient hardware implementation. Then, we present an SRAM macro that efficiently accelerates the algorithm by realizing key operations such as L1 distance calculation and Winner-Take-All (WTA) operation through mixed-signal computation circuits. Fabricated in 40nm LP CMOS technology, the design demonstrates 27.7 TOPS/W maximum energy efficiency, while achieving 93.40% and 98.28% classification accuracy for 5-way 1-shot and 5-way 5-shot learning on the Omniglot dataset, which closely matches the accuracy of the baseline algorithm.

Section: Winner-take-all Circuitmentioning

confidence: 99%

“…Another approach in [12] implements Loser-take-all (LTA) circuit that mirrors the minimum input current at the output node. The WTA circuit in [13] uses positive feedback between NOR gates to find a winner.…”

Section: Introductionmentioning

confidence: 99%

An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network

Lee

IEEE Trans. Circuits Syst. II

et al. 2022

“…Its simplicity that leads to space savings on integrated chips has distinguished it technologically. Many improvements to the Lazzaro circuit have been proposed in the meantime [ 22 , 23 ], but the basic principle and configuration have not changed.…”

Section: Introductionmentioning

confidence: 99%

“…Integrated circuit technology, engaged in a race to reduce the size of chips and circuits, cannot ensure the strict identity of the parameters on the same chip or on different chips. Thus appears the so-called “mismatch”—[ 22 , 23 , 24 , 25 ], whose size is a criterion for the performance of the chips. It is all the more important as the circuit works with lower currents.…”

Section: Introductionmentioning

confidence: 99%

Decision Levels and Resolution for Low-Power Winner-Take-All Circuit

Costea

2023

Sensors

Sensors in many applications must select the largest element in a sequence of currents. This can be performed in an analog way by the Winner-Take-All (WTA) circuit. This paper considers the classic version of the WTA Lazzaro circuit, working with MOS devices in a subthreshold regime. Since the separation of the gainer by analytically computable “decision levels” has recently been introduced, this paper aims to numerically verify and discuss these levels and their dependence on circuit and device parameters. For VT, the threshold voltage of MOS devices, which is primarily responsible for differences between components (mismatch), its relationship with the output voltages is theoretically demonstrated and numerically checked.

“…Considering the input signal, WTA circuits are divided into voltage and current mode, which are called the voltage WTA circuits and the current WTA circuits, respectively. In terms of architecture, WTA circuits can be classified into two general categories of analog output [6] and digital output (positive feedback) [7,8], that the former follows the largest input signal at any given moment of the time, while the latter identifies the winner. In literature, several structures have been presented to improve the performance of the current-input analog WTAs [4,6].…”

mentioning

confidence: 99%

A low‐voltage and low‐power current‐mode winner‐take‐all (maximum) circuit

Shadmehri,

Saberi,

Rahiminejad

et al. 2023

Electronics Letters

Self Cite

In this Letter, a new low‐voltage and low‐power current‐mode winner‐take‐all (WTA) circuit is proposed. The proposed circuit is able to operate with a low supply voltage requirement while exhibiting a high accuracy. Moreover, the sensitivity of the circuit to the process variations and mismatches is improved. The proposed WTA circuit is designed and simulated in a 65‐nm technology with a supply voltage of VDD = 0.9 V. The post‐layout simulation results show that the power consumption of the proposed circuit is about 72 μW with the input dynamic range of 40 μA.