A low-voltage high-linearity UWB down-conversion mixer in 0.18-μm CMOS technology

Abstract

A low voltage high-linearity ultra-wideband CMOS down-conversion mixer is designed. The third-order transconductance (g m3 ) cancellation techniques are utilized for improvement of the linearity of the mixer. In addition, the active loads and a switched buffer stage are used to increase the conversion gain. The designed mixer simulated by TSMC 0.18-µm CMOS technology achieves DC power consumption of 1.9 mW, maximum input third-order intercept point (IIP3) of +12dBm, conversion gain of 11 dB and double side-band noise figure (DSB NF) of 14.3 dB. A Gilbert-cell mixer was designed using the proposed method to further estimate the linearity in TSMC 0.18-µm CMOS process. The 3-dB RF frequency bandwidth is from 8 to 10 GHz with an IF of 1 MHz, and consumes 1.59 mA of current from a 1.2 V voltage supply.