A Low-Voltage Current Reference with High Immunity to EMI

Cordova, David; Toledo, Pedro; Fabris, Eric

doi:10.1145/2660540.2660989

Cited by 5 publications

(2 citation statements)

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“…The susceptibility of current mirrors has been investigated, and some solutions to increase their EMI-robustness have been proposed in the literature [23][24][25][26][27][28][29][30]. The typical approach is based on capacitors properly placed to implement a filter and attenuate the EMI [23][24][25][26][27][28]. Anyhow, all these solutions refer to transistors nominally operating in the saturation region (above threshold).…”

Section: Rfi Effect On Current Mirrorsmentioning

confidence: 99%

Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

Aiello

2021

JLPEA

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The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

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Section: Rfi Effect On Current Mirrorsmentioning

confidence: 99%

Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

Aiello

2021

JLPEA

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“…4, is an all-MOS implementation of the self-biased current reference (SBCR) presented in [5]. The core of the SBCR is composed by the self-cascode MOSFET (SCM M 1 -M 2 ) and the bootstrapped structure (M 3 -M 4 -M 5 ), both with zero-V T active loads (M ZV T 1 -M ZV T 2 ).…”

Section: A Voltage Reference Circuitmentioning

confidence: 99%

A 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference

Cordova

Toledo

Klimach

et al. 2016

2016 IEEE 7th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

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Electromagnetic Interference (EMI) degrades the performance of voltage and current references, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm 2 of silicon area while consuming just 1.15 µW . Postlayout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/ o C, for the temperature range from -55 to 125 o C. An EMI source of 4 dBm (1 Vpp) injected in the power supply , according to the Direct Power Injection (DPI) standard, yield in a maximum DC Shift and Peak-to-Peak ripple of -0.17 % and 822 µVpp, respectively.

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