A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

Greenley, B.R.; Veith, R.; Chang, Dong-Young; Moon, Un-Ku

doi:10.1109/tcsii.2005.843595

Cited by 21 publications

(8 citation statements)

References 6 publications

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“…Further, most of the DAC are now fabricated with the technology of standard CMOS process to satisfy the condition of an Intellectual Property (IP) in a large CMOS SOC. There exist many kinds of design technique to implement a CMOS DAC such as a decoder based design with an operational amplifier, a current steering type design, a cyclic or a charge redistributed type design, and so on [1][2][3][4][5][6][7][8]. Among them, a current steering type design is widely used because it has the capability of driving resistive loads without any special buffers like operational amplifiers and it has the suitability for simple CMOS implementation.…”

Section: Introductionmentioning

confidence: 99%

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

Lee

Song

2014

Analog Integr Circ Sig Process

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A 10-bit CMOS cyclic D/A converter based on an improved Johnson counter and a capacitor swapping technique is described. In order to reduce the capacitor mismatching errors, we propose that two capacitors are alternately swapped depending on the input data. Further, a half differential architecture to reduce offset errors and an improved Johnson counter are also discussed. With a 0.35 lm Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 240 lW at 3.3 V power supply. The measured INL and DNL are within ±0.7 and ±0.7 LSB, respectively.

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Section: Introductionmentioning

confidence: 99%

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

Lee

Song

2014

Analog Integr Circ Sig Process

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“…The design of DACs based on standard CMOS technologies has been pursued to overcome these constraints with some success [2][3][4][5][6][7]. Although each of the converters have some attractive features, in the form of either consuming low power [2][3][4][5], or possessing good dynamic performance [6], all of them consist of segmented or matrix architecture, rendering a complexity to the D/A converter circuit.…”

Section: Introductionmentioning

confidence: 99%

“…Although each of the converters have some attractive features, in the form of either consuming low power [2][3][4][5], or possessing good dynamic performance [6], all of them consist of segmented or matrix architecture, rendering a complexity to the D/A converter circuit.…”

Section: Introductionmentioning

confidence: 99%

A low voltage 8-bit digital-to-analog converter using floating gate MOSFETs

Sehgal

Rajput

2008

Analog Integr Circ Sig Process

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A new low voltage digital-to-analog conversion (DAC) architecture is proposed using weighted summation of voltages at the input terminals of a Floating Gate MOSFET (FGMOS). An 8-bit DAC has been designed based on this architecture and its simulation results are provided to verify its operation at ±1.0 V. The circuit possesses good accuracy, fast dynamic performance and low power consumption. The circuit operation was verified through SPICE simulations carried out using 0.13 lm CMOS technology.

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“…One major design challenge is to achieve high static and dynamic linearity in the existence of inevitable process variations, e.g., the systematic V th gradient across the wafer and the random device mismatch. While an elaborate analysis about the technology dependent intrinsic resolution could be found in [1], various layout techniques [2] [3] have been developed to enhance the achievable resolution by canceling out the process variation gradient. However, both the required large current source array and the complex routing introduce parasitic capacitance that poses negative impact on the dynamic performance.…”

Section: Introductionmentioning

confidence: 99%

A self-testing and calibration technique for current-steering DACs

Huang

2008

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In selftesting mode, the controller executes the self-testing algorithm to characterize the DAC higher bits and computes the calibration information. In function mode, it produces the inputs to the duplicated lower bits for calibration. To validate the idea, a 14-bit prototype has been fabricated using TSMC 0.35 µm technology. The measurement results show that INL, DNL, and SFDR are significantly improved.

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A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

Cited by 21 publications

References 6 publications

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

A low voltage 8-bit digital-to-analog converter using floating gate MOSFETs

A self-testing and calibration technique for current-steering DACs

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