A low power video-rate pyramid VQ decoder

Fault Secure Encoder and Decoder with Clock Gating

“…This fault secure detector can verify the correctness of the encoder and corrector operation [11,13]. To address memory, ring counter is used [3]. This ring counter employs clock gating technique to reduce power consumption.…”

A 1.1-V 9.9-mW MC-CDMA Downlink Baseband Receiver IC for Next-Generation Cellular Communication Systems

“…For data scheduling in FFT operation, longer delay buffers are implemented with two single-port SRAM modules, which save both area and power compared to one two-port SRAM module. Nonetheless, delay buffers shorter than 64 are implemented by D flip-flops that are configured in a pointer FIFO configuration to eliminate excessive data transitions [6]. A ring counter with only one active cell is used and shared for several short delay buffers to activate one word for read-out and one word for write-in.…”

Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing

“…Typically, it is the MSE value that is minimized, where the MSE is defined as (3) where is the expectation operator. If the error is assumed to be an ergodic process, then the sample average of can be approximated by its time average, which is given by (4) where is the window over which the squared error is averaged. It can be shown [29] that if the input signal is a wide-sense stationary (WSS) white process (samples of are uncorrelated), then the minimum MSE is given by (5) where is the desired signal power, is the input signal power, and are the optimum coefficients.…”

“…Energy minimization techniques have been proposed at all levels of the design hierarchy beginning with algorithms and architectures and ending with circuits and technological innovations. Existing techniques include those at the algorithmic level (such as strength reduction [1]- [3] and variable-length vector quantizer (VQ) [4]), architectural level (such as pipelining [5], [6] and parallel processing [6]), logic (logic minimization [7], [8] and precomputation [9]), circuit (reduced voltage swing [10] and adiabatic logic [11]) and Manuscript received July 1, 1998; revised November 15, 1998. This work was supported by the National Science Foundation under CAREER Award MIP 96-23737, and by the Defense Advanced Research Projects Agency under Contract DABT63-97-C-0025.…”