A low-power pipelined MAC architecture using Baugh-Wooley based multiplier

Warrier, Rakesh; Zhang, Wei

doi:10.1109/gcce.2014.7031169

Cited by 14 publications

(5 citation statements)

References 6 publications

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“…MAC's simple operation is to multiply two variables (X i and Y i ) and add the product to the last cycle's output. Therefore, the MAC architecture includes the key operational blocks of a multiplier, adder, and register/accumulator [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. The multiplier multiplies the two input operands; the adder attaches the multiplier's output to the previous cycle's result, and the register or accumulator preserves the final addition output.…”

Section: Introduction To Multiply and Accumulate (Mac) Architecturementioning

confidence: 99%

“…In recent years, different researchers have done several works [2][3][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. Reference [22] proposes a high throughput MAC architecture that promises the optimized area in 2007.…”

Section: Introduction To Multiply and Accumulate (Mac) Architecturementioning

confidence: 99%

“…NCSim and RTL Compiler are used in the implementation. In the year 2014, reference [9] proposes a "low-power Baugh-Wooley multiplier-based MAC" unit. A pipelined-based architecture has been proposed in this work.…”

Section: Introduction To Multiply and Accumulate (Mac) Architecturementioning

confidence: 99%

See 2 more Smart Citations

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

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In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −(7.96872) 10 to + (7.96872) 10 . The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as "block enabling" and "clock gating" are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.

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Section: Introduction To Multiply and Accumulate (Mac) Architecturementioning

confidence: 99%

Section: Introduction To Multiply and Accumulate (Mac) Architecturementioning

confidence: 99%

See 1 more Smart Citation

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

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“…The implementation is done on NCSim and RTL Compiler. Warrier et al proposed a low power Baugh-Wooley multiplier-based unit in 2014 [8]. A pipelined based architecture has been proposed in this work.…”

Section: Introductionmentioning

confidence: 99%

Bulletin of the Polish Academy of Sciences: Technical Sciences

Sarma¹,

Bhargava²,

Jain³

2020

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Digital system algorithms such as FFT algorithms, convolution, image processing algorithm, etc. deploy Multiply and Accumulate (MAC) unit as an evaluative component. The efficiency of a MAC typically relies on the speed of operation, power dissipation, and chip area along with the complexity level of the circuit. In this research paper, a power-delay-efficient signed-floating-point MAC (SFMAC) is proposed using Universal Compressor based Multiplier (UCM). Instead of having a complex design architecture, a simple multiplexer-based circuit is used to achieve a signed-floating output. The 8£8 SFMAC can take 8-bit mantissa and 3-bit exponent and therefore, the input to the SFMAC can be in the range of -(7.96875) 10 to +(7.96875) 10 . The design and implementation of the proposed architecture is executed on the Cadence Spectre tool in GPDK 90 nm and TSMC 130 nm CMOS, which proves as power and delay efficient.

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“…In [199], the authors proposed reducing the power consumption by bypassing the multiplier and accumulator depending on consecutive input bits. Clock gating method was introduced in [207] to minimize the power utilization of a multiplier in a MAC unit without using additional circuitry. The proposed DSP architecture also extends this approach by allowing each pipeline stage to be independently clock gated, thus providing finer control over power consumption.…”

Section: Dsp Power Reduction Techniquementioning

confidence: 99%

Design and optimization of DSP architectures for multi-context FPGA with dynamic reconfiguration

Warrier¹

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Field Programmable Gate Arrays (FPGAs) are now widely adopted as hardware accelerators due to their inherent parallel processing capability. However, the suboptimal logic utilization and large reconfiguration latency in conventional singlecontext FPGAs pose constraints on their usage for applications like adaptive control systems in vehicles, software defined radio where frequent context switching or resource sharing between tasks are required. As such, multi-context FPGAs with dynamic reconfiguration capability have been introduced with the aim to allow rapid reconfiguration of the FPGA, and hence increase the effective logic density. The current generation of multi-context FPGAs typically use a dynamic reconfigurable architecture based on static Random Access Memory (RAM) to implement multiple configuration planes that enable fast switching between contexts. The main challenge of these types of multi-context FPGAs are limited on-chip storage and relatively long reconfiguration latency (of the order of milliseconds). With technology driving down to nano scale, new generations of hybrid multi-context FPGA architectures, such as the CMOS/NAnoTechnology reconfigURablE architecture (NATURE) that use on-chip nano RAMs to store multiple configurations to enable extremely fast runtime reconfiguration (of the order of pico seconds) have been developed. This type of FPGA enables cycle-by-cycle reconfiguration and temporal logic folding resulting in improved logic density and area delay product by more than an order of magnitude compared to traditional FPGAs. However, the fine granularity of this type of architecture limits its usage as a high performance hardware accelerator that implements compute intensive arithmetic operations.

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A low-power pipelined MAC architecture using Baugh-Wooley based multiplier

Cited by 14 publications

References 6 publications

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Bulletin of the Polish Academy of Sciences: Technical Sciences

Design and optimization of DSP architectures for multi-context FPGA with dynamic reconfiguration

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