A Low-Power Multiplier Using Adiabatic CPL Circuits

Ling, Wang; Hu, Jianping; Dai, Jiao

doi:10.1109/isicir.2007.4441786

Cited by 8 publications

(11 citation statements)

References 11 publications

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“…Active areas for cpl-ad [16] and the proposed xb-ad circuits are 119.60µm 2 , and 43.10µm 2 , respectively, (64% increase for cpl-ad). Both circuits were optimized for the lowest energy delay product.…”

Section: Comparative Evaluationmentioning

confidence: 99%

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Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications

Garcia-Montesdeoca

Montiel–Nelson

Nooshabadi

et al. 2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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This paper presents the design of an adiabatic/bootstrapped CMOS driver (xb-ad) using complementary pass-transistor logic (CPL) and a four-phase power clock. The proposed xb-ad uses a bootstrapped load driven circuit with PMOS and NMOS transistors driven by an NMOS evaluation logic block. When implemented on a 65nm CMOS 1V technology, under the large capacitive loading condition (16pF), xb-ad performs better than the reference adiabatic circuit (cpl-ad) in terms of active area (64%), and energydelay product (39%). Moreover, xb-ad supports 10 times higher output capacitive load without any additional circuit sizing than cpl-ad.

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Section: Comparative Evaluationmentioning

confidence: 99%

“…2, shows the circuit diagram of the proposed xb-ad. The proposed circuit modifies the output stage of the bootstrapped adiabatic CPL circuit in [16] to improve its driving capability in the presence of large loads. The criteria chosen for comparison are delay, energy consumption, energy-delay product and active area.…”

Section: The Driver Circuit Structurementioning

confidence: 99%

Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications

Garcia-Montesdeoca

Montiel–Nelson

Nooshabadi

et al. 2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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“…The 4-bit ripple carry adder consists of four cascaded full adders [8] shown in Fig. 3(a) The simulation waveforms shown in Fig.…”

Section: -Bit Ripple Carry Addermentioning

confidence: 99%

“…4 (a). For the implementation of binary counter, we have used the sizes of all the gates [8] and flip flops as equal and in which the sizes of bootstrapping transistor are larger than the size of nmos transistor in single gate. For this, we have used four clock pulses namely 1, 2, 3 and 4.…”

Section: -Bit Binary Countermentioning

confidence: 99%

Low Power Combinational and Sequential Circuits with Adiabatic Complementary Pass-Transistor Logic (ACPL)

Bhikshalu¹,

Kumar²

2016

IJCA

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This paper presents low-power characteristics of adiabatic complementary pass-transistor logic (ACPL) using four-phase AC power supply. Adiabatic CPL circuits consist of pure NMOS transistors, use CPL blocks for evaluation and bootstrapped NMOS switches to eliminate non-adiabatic loss of output loads. In this paper, combinational circuit (4-bit ripple carry adder) and sequential circuit (4-bit binary counter) is realized with adiabatic CPL.These combinational and sequential circuits have been simulated in CADENCE design tool at 90nm technology and simulation results shows that the adiabatic CPL 4-bit ripple carry adder achieve power savings of 80% with PAL-2N logic and adiabatic CPL 4-bit binary counter achieve power savings of 52% with CMOS logic for clock frequencies from 50 to 300 MHz.

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“…Therefore, to achieve the evaluation and give a valid digital output, a comparator is needed. In this regard, very compact low-voltage comparators using only two transistors have been proposed [3] since reduced transistor count and low-voltage is the most straightforward way to achieve low power [4].…”

Section: Introductionmentioning

confidence: 99%

Noise margin and short-circuit current in FGMOS logics

Cisneros-Sinencio

Díaz-Sánchez

Ramírez-Angulo

2011

IEICE Electron. Express

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Even when floating-gate logics are very-low-voltage circuits, as power supply is reduced, large fan-in FGMOS gates are prone to fail. Thus, determining the negative impact of noise margin and short-circuit current in this type of circuits is crucial to achieve optimal operation for a particular application. For this reason, a systematic and reliable technique for obtaining the correlation between fan-in and supply voltage, simultaneously considering noise margin and short-circuit current, is proposed.

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A Low-Power Multiplier Using Adiabatic CPL Circuits

Cited by 8 publications

References 11 publications

Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications

Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications

Low Power Combinational and Sequential Circuits with Adiabatic Complementary Pass-Transistor Logic (ACPL)

Noise margin and short-circuit current in FGMOS logics

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