A low power Ku phase locked oscillator in low cost 130 nm CMOS technology

Magnani, Alessandro; Borgarino, M.; Viallon, Christophe; Parra, T.; Jacquemod, G.

doi:10.1016/j.mejo.2014.04.013

Cited by 5 publications

(2 citation statements)

References 26 publications

(28 reference statements)

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“…These solutions are more complicated, and they also do not solve the issue fully. To combat both of the issues, PFD design without the reset signal had been implemented and has been proved to be quite satisfactory [11]. However, as the solution offered is for dynamic design, it is suitable only for high-speed applications.…”

Section: Related Previous Workmentioning

confidence: 99%

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Koithyar

Ramesh

2020

IET Circuits, Devices & Systems

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In this article, a novel design is presented, for an Integer-N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.

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Section: Related Previous Workmentioning

confidence: 99%

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Koithyar

Ramesh

2020

IET Circuits, Devices & Systems

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“…Overall comparison of resultsParameterRen et al8 Chen et al10 Magnani et al11 Erfani-Jazi et al 12 This Work : CP, charge pump; D-FF, D flip-flops; PD, phase detector; PFD, phase frequency detector; QRO, quadrature ring oscillator; TG, transmission gate; TSPC, true single-phase clock; VCO, voltage-controlled oscillator.…”

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confidence: 99%

A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

Koithyar

Ramesh

2018

Circuit Theory & Apps

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In this paper, we present a new design of phase frequency detector (PFD) without reset, such that the blind zone and dead zone issues in the phase locked loop are annihilated. The PFD is designed using transmission gate-based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies. Thus, the continuous pulses that get produced by the conventional NAND gate-based latches are avoided, leading to reduced power consumption of the PFD. The charge pump makes use of an op-amp used as a buffer, to reduce the current mismatch. The loop filter used is of second order, and the voltage-controlled oscillator is of conventional current-starved type. The divider makes use of true single-phase clock latches. It was found that the phase locked loop with new design of PFD, compared with the conventional design, consumes 27% lesser power, and the lock time is decreased by 79%. In addition, it was found that the control voltage swing is reduced by 71%, which leads to much lesser spur content at the output of the voltage-controlled oscillator.KEYWORDS blind zone, charge pump (CP), dead zone, divider, loop filter, phase frequency detector (PFD), voltagecontrolled oscillator (VCO)

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Comprehensive analysis of linear phase frequency detectors in phase-locked loops

Sivaraaj,

K.K.

2024

AEU - International Journal of Electronics and Communications

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A low power Ku phase locked oscillator in low cost 130 nm CMOS technology

Cited by 5 publications

References 26 publications

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

Comprehensive analysis of linear phase frequency detectors in phase-locked loops

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