2009
DOI: 10.1109/tcsii.2009.2023281
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A Low-Power Integrated Circuit for Interaural Time Delay Estimation Without Delay Lines

Abstract: A low-power IC for the estimation of the delay between two infinitely clipped (digital) signals is designed and implemented in a 0.35-μm standard CMOS technology. The proposed circuit is based on a sliding-mode control system and does not need past values of the inputs, which are usually stored using chains of digital registers or analog delay lines and significantly increase the power consumption. The IC is intended to work in ultralow-power miniature sensor network nodes performing localization in the audio … Show more

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Cited by 5 publications
(9 citation statements)
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References 12 publications
(17 reference statements)
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“…Thus, this IC should be adequate to capture the bearing angle of a gunshot sound. Besides, the energy required by the IC to perform the calculation is equal to or even lower than the best result reported so far in the literature [8], owing in great part to its fastest convergence time. …”
Section: Control Fsm Not Shownmentioning
confidence: 71%
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“…Thus, this IC should be adequate to capture the bearing angle of a gunshot sound. Besides, the energy required by the IC to perform the calculation is equal to or even lower than the best result reported so far in the literature [8], owing in great part to its fastest convergence time. …”
Section: Control Fsm Not Shownmentioning
confidence: 71%
“…Considering a 200 Hz signal, the energy required for an estimation is E ¼ 0.5 × 6 × 9.8 mW/200 Hz ¼ 147 nJ. For the sake of comparison, the IC in [8] requires 156nJ per estimation (comparisons based on a 150 ms convergence time for a 300 ms delay estimation, as defined in [8], with a power consumption of 1.04 mW). This system assumes periodic, stationary signals 3 Convergence time is the longest one required by LMS-adaptation rule used by IC [5] Conclusions: The presented IC is able to estimate the ITD of a couple of signals captured with two microphones within six edges of the incoming signal (15 ms for a 200 Hz input signal, 3.5 ms for a 1 kHz input signal), with a precision of 5 us.…”
Section: Control Fsm Not Shownmentioning
confidence: 99%
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“…The performance of the system, with low power CMOS VLSI design, is of the order of 1° error margin and similar standard deviation for the bearing angle estimation (Cauwenberghs et al, 2005; Julian et al, 2006; Pirchio et al, 2006). A very low power implementation for interaural time delay (ITD) estimation without delay lines with the same ASU unit is reported by Chacon-Rodriguez et al with an estimation error in the low single-digit range (Chacon-Rodriguez et al, 2009). …”
Section: Introductionmentioning
confidence: 97%