A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm

Parlak, Mustafa; Hamzaoğlu, İlker

doi:10.1109/ahs.2007.7

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Cited by 7 publications

(2 citation statements)

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“…While much work [14,21] in this field reports that clock gating reduces power consumption, there is at least one paper [5] which reports the contrary. Moreover, most results from previous work are obtained by vendor's simulators such as XPower.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable design with clock gating

Osborne¹,

Luk²,

Coutinho³

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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This paper describes an approach for developing energyoptimized run-time reconfigurable designs which benefit from clock gating. The approach is applied to two techniques: multiplexer-based reconfiguration, and reconfigurable wordlength optimization. The conditions under which this approach would be preferable to bit-stream reconfiguration are derived. Various case studies, such as ray tracing, guitar string simulation and matrix-vector multiplication, are used to illustrate this approach.

show abstract

Section: Introductionmentioning

confidence: 99%

Reconfigurable design with clock gating

Osborne¹,

Luk²,

Coutinho³

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

View full text Add to dashboard Cite

show abstract

“…In this paper, we present two efficient and low power H.264 DBF hardware implementations that can be used as part of an H.264 video encoder or decoder for portable applications [5,6]. The first implementation (DBF_4×4) starts filtering the available edges as soon as a new 4x4 block is ready by using a novel edge filtering order.…”

Section: Introductionmentioning

confidence: 99%