A Low-Power, High-Fidelity Stereo Audio Codec in 0.13 $\mu$m CMOS

Design of a CMOS Single Bit 3rd Order Delta-Sigma Modulator with Switched Operational Amplifier

“…의 VLSI 공정 기술로는 약 0.1%의 수동소자 정합 특성을 제공하므로 15비트 이상의 해상도를 얻기 위해서는 고가의 레이저 트리밍 기법 등을 이용해 야만 한다 [1,2] . 이러한 단점 때문에 나이키스트 변환기보다 훨씬 높은 샘플링 주파수를 사용하는 오버샘플링 기법의 델타시그마 변조기에 많은 관심이 집중되고 있다 [3] .…”

Analysis and design of an adaptive-supply class H audio power amplifier for mobile devices

“…Another design which embody the similar consideration is depicted in Fig 2.13 [29]. In for the two transistors can be reduced to be less than 1 mV.…”

“…In view of the properties and trade-offs of class AB amplifier design, many novel structures are proposed for improvement. Instead of tangling with the efficiency and headroom voltage trade-offs, previously reported works mainly focused on the method for reducing the quiescent power consumption [13,[17][18][19][28][29][30]. One way of doing it is through reducing the minimum operating voltage of the output stage [17,18,28], while the other way is to reduce the quiescent current variations through process corners [19,29,30].…”

“…Ideally if the gate voltages of the two transistors are matched then the output stage current I Q is well defined. However, due to the diode-connected structure of M Na , the drain-to-source voltages of the two transistors are different and can result in large I Q variations as large as ±26% over different process corners [29]. Therefore certain design techniques are needed to reduce the CLM-induced quiescent current variation.…”

“…Thus, it significantly reduces the current variation due the CLM effect. According to reference [29], the output stage quiescent current variation over different PVT corners is reduced to ±1.5%.…”