A low-power fully differential cyclic 9-bit ADC

An 8-bit 500kS/s semi-digital cyclic ADC with time-mode residue voltage generation

“…The final digital output shows D out = 00110011, which corresponds to 0.2V for full scale input range of 1V. [2] and [3], and comparable to [1]. This is due to the low power operation owing to the reduced supply voltage and on/off control of the current sources.…”

“…Along with the successive approximation (SAR) ADCs, cyclic ADCs that generate the output bit for each operation cycle are widely used for sensor readout blocks for portable bio-medical devices [1][2][3]. Cyclic ADCs are compact, and can operate with low power which is suitable for low speed and medium to high resolution data acquisition applications.…”

Design of low-power voltage/current references and supply voltage for 9-bit fully differential ADC

“…The setting time is defined by the speed of the ADC. The output voltage of the ADC, presented in [11], settles within 1.5 µs so the buffers must settle much faster and T S is chosen to be 0.5 µs. According to (5) for the 9-bit resolution and T S =0.5 µs, the GBW is ≈2 MHz.…”

“…This paper focuses on the design of supply voltage and fully differential reference voltages (presented in [10]) for the fully differential 9-bit ADC implemented in 0.18 µ CMOS process. The ADC is presented in [11]. Fig.…”

An 11‐μ W, 9‐bit fully differential, cyclic/algorithmic ADC in 0.13 μm CMOS

“…The proposed 9‐bit fully differential cyclic ADC, presented in , is shown in Figure . Compared with , the ADC presented in this paper is implemented in 0.13 μm CMOS process and has the fully cancelled offset. Modification in design that enables cancellation of the offset voltage is mentioned later in the text.…”