A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

Kotabe, Akira; Osada, Kensuke; Kitai, N.; Fujioka, M.; Kamohara, S.; Moniwa, Masahiro; Morita, Sadayuki; Saitoh, Y.

doi:10.1109/jssc.2005.845553

Cited by 22 publications

(13 citation statements)

References 11 publications

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“…To satisfy the above conditions, when '0' is stored in the cell during the idle mode, similar to the technique used in [5,9,10,11], we used the leakage current of access transistors, especially the subthreshold current of access transistors, including I SD-M1 , I SD-M2 , I SD-M3 and I SD-M4 . Therefore, to satisfy the above conditions, during the idle mode as shown in Fig.…”

Section: Right Sidementioning

confidence: 99%

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

Mazreah¹,

Shalmani²

2012

Microelectronics Journal

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Section: Right Sidementioning

confidence: 99%

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

Mazreah¹,

Shalmani²

2012

Microelectronics Journal

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“…These on-chip caches are usually implemented using arrays of densely packed SRAM cells for high performance [1]. A six-transistor SRAM cell (6T SRAM cell) is conventionally used as the memory cell [2]. However, the 6T SRAM cell produces a cell size an order of magnitude larger than that of a DRAM cell, which results in a low memory density [2].…”

Section: Introductionmentioning

confidence: 99%

“…A six-transistor SRAM cell (6T SRAM cell) is conventionally used as the memory cell [2]. However, the 6T SRAM cell produces a cell size an order of magnitude larger than that of a DRAM cell, which results in a low memory density [2]. Therefore, conventional SRAMs that use the 6T SRAM cell have difficulty meeting the growing demand for a larger memory capacity in mobile applications [2].…”

Section: Introductionmentioning

confidence: 99%

“…However, the 6T SRAM cell produces a cell size an order of magnitude larger than that of a DRAM cell, which results in a low memory density [2]. Therefore, conventional SRAMs that use the 6T SRAM cell have difficulty meeting the growing demand for a larger memory capacity in mobile applications [2]. Furthermore, in the conventional SRAM cell, because one of two bit-lines must be discharged to low regardless of written value, the power consumption in both writing '0' and '1' are the same [1].…”

Section: Introductionmentioning

confidence: 99%

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A low power and high density cache memory based on novel SRAM cell

Mazreah

Romani²,

Manzuri

et al. 2009

IEICE Electron. Express

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Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor (4T) SRAM cell for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules and delay access of a cache based on new 4T SRAM cell is 32% smaller than a cache based on 6T SRAM cell. Also the dynamic and static power consumption of new cell is 40% and 20% smaller than 6T SRAM cell, respectively.

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“…Alternative solutions to dynamically vary the threshold voltage are proposed in [12] and [13] where it is demonstrated how the off drain-to-source current can be significantly reduced with respect to the conventional SRAM structure by reverse body biasing both nMOS and pMOS devices. Finally, in [15]- [17] the possibility of acting on the bit lines or on the word line of the SRAM cell is examined to reduce the leakage power consumption.…”

mentioning

confidence: 99%

Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories

Frustaci

Corsonello

Perri

et al. 2006

IEEE Trans. VLSI Syst.

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The techniques known in literature for the design of SRAM structures with low standby leakage typically exploit an additional operation mode, named the sleep mode or the standby mode. In this paper, existing low leakage SRAM structures are analyzed by several SPEC2000 benchmarks. As expected, the examined SRAM architectures have static power consumption lower than the conventional 6-T SRAM cell. However, the additional activities performed to enter and to exit the sleep mode also lead to higher dynamic energy. Our study demonstrates that, due to this, the overall energy consumption achieved by the known low-leakage techniques is greater than the conventional approach. In the second part of this paper, a novel low-leakage SRAM cell is presented. The proposed structure establishes when to enter and to exit the sleep mode, on the basis of the data stored in it, without introducing time and energy penalties with respect to the conventional 6-T cell. The new SRAM structure was realized using the UMC 0.18-m, 1.8-V, and the ST 90-nm 1-V CMOS technologies. Tests performed with a set of SPEC2000 benchmarks have shown that the proposed approach is actually energy efficient.

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A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

Cited by 22 publications

References 11 publications

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

A low power and high density cache memory based on novel SRAM cell

Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories

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