2009 IEEE International Conference on RFID 2009
DOI: 10.1109/rfid.2009.4911177
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A low-power dual-clock strategy for digital circuits of EPC Gen2 RFID tag

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Cited by 7 publications
(2 citation statements)
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“…Taking into account that both encoding formats require a transition in the middle of the transmitted symbol, it is necessary to have a clock of at least the double BLF. Since there is no rigid duty-cycle requirement imposed on the clock of 2×BLF, a simple clock doubler [4], [6], which is composed of a delay unit and a XOR gate, is implemented to multiply the BLF by 2. Although the fractional N+0.5 frequency divider helps the baseband processor improve the precision of BLF calibration, it has a defect that makes the duty-cycle of the output clock deviate from 50%.…”
Section: ) Frequency Variation Independent Blf Calibrationmentioning
confidence: 99%
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“…Taking into account that both encoding formats require a transition in the middle of the transmitted symbol, it is necessary to have a clock of at least the double BLF. Since there is no rigid duty-cycle requirement imposed on the clock of 2×BLF, a simple clock doubler [4], [6], which is composed of a delay unit and a XOR gate, is implemented to multiply the BLF by 2. Although the fractional N+0.5 frequency divider helps the baseband processor improve the precision of BLF calibration, it has a defect that makes the duty-cycle of the output clock deviate from 50%.…”
Section: ) Frequency Variation Independent Blf Calibrationmentioning
confidence: 99%
“…And it's well known that the decision of a tag's clock frequency is crucial to working distance [6]. However, a huge challenge concerning the clock frequency is that an accurate frequency cannot be achieved as a result of process, voltage and temperature (PVT) variations.…”
Section: Introductionmentioning
confidence: 99%