A low-power concurrent multiplier-accumulator using conditional evaluation

Development of a large word-width high-speed asynchronous multiply and accumulate unit

“…The output was the 72-bit 2 s -complement result along with an overflow signal. A comparison between the NCL MAC developed in [10] and these other asynchronous MACs [6][7][8] is shown in Table 1.…”

“…This MAC employs the parallel Booth2 algorithm, and has an average cycle time of about 90 ns. A third self-timed MAC described in [8] was designed in single-ended dynamic logic [9], utilizing conditional evaluation along with the traditional Array multiplication algorithm. Conditional evaluation allows for rows with a zero bit product to be multiplexed around, to reduce energy and delay.…”

“…Conditional evaluation allows for rows with a zero bit product to be multiplexed around, to reduce energy and delay. In [8] a 16+8 Â 8 MAC was simulated using 3.3 V, 0.35 mm CMOS technology, to determine the average cycle time of 7.8 ns. This delay information was then used in [8] to estimate the average cycle time for a 32+16 Â 16 MAC as approximately 24 ns.…”

NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation

“…This MAC employs the parallel Booth2 algorithm, and has an average cycle time of about 90 ns. A third self-timed MAC described in [8] was designed in single-ended dynamic logic [23], utilizing conditional evaluation along with the traditional Array multiplication algorithm. Conditional evaluation allows for rows with a zero bit product to be multiplexed around, to reduce energy and delay.…”

“…Conditional evaluation allows for rows with a zero bit product to be multiplexed around, to reduce energy and delay. In [8] a 16+8×8 MAC was simulated using …”