A low-power coarse-fine time-to-digital converter in 65nm CMOS

Abstract

A low-power coarse-fine time-to-digital converter (TDC) with a wide dynamic range and high time resolution is presented in this paper. The first stage is based on a buffer delayline chain. Then the input signal and its adjacent reference clock are injected into a Vernier-delay-line (VDL) time-quantizer at the second stage for a finer resolution. The proposed architecture can provide high resolution with less hardware compared to the one-stage VDL TDC with the same dynamic range. A powersaving circuit is employed achieving >50% power reduction. A delay-tunable buffer is utilized to tolerate the process, voltage and temperature (PVT) variations. The design's parameter has been simulated and optimized in a 65nm CMOS process. The simulation results show a minimum time resolution of 6.15 ps and a maximum dynamic range of 1260 ps corresponding to 8bits resolution. The power consumption is 2.5 mW with the reference frequency of 40MHz.