A Low-Power ASIC Signal Processor for a Vestibular Prosthesis

Abstract

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm2 and consumes 1.24 mW when supplied with ± 1.6 V.

Vestibular prosthesis: from basic research to clinics

“…The performance of this new device was like that previously reported with larger devices, with the advantage of having a much smaller, implantable device and lower power consumption. Recent developments have also used ASICs with more complex mathematical processing ( Töreyin and Bhatti, 2016 ).…”