A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay Lines

Angeli, Nico

doi:10.1109/icecs.2018.8617948

Cited by 10 publications

(1 citation statement)

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“…To achieve a fine delay, the delay unit of FDL is composed of an inverter and a capacitor. The capacitor is implemented by a transmission gate (TG), which generates a small propagation delay difference by the difference in load effect between its on and off states [24], thus achieving a fine delay. The cascaded inverter in the fine delay unit is used to restore the driving capability of the delay path.…”

Section: The Three-stage Digitally Controlled Delay Linementioning

confidence: 99%

A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit

et al. 2023

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A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0∘ output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μm CMOS process with a 0.072 mm2 core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps.

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Section: The Three-stage Digitally Controlled Delay Linementioning

confidence: 99%