A low-power 5 GHz CMOS LC-VCO optimized for high-resistivity SOI substrates

Delatte, Pierre; Picun, Gonzalo; Demeûs, Laurent; Simon, Pascal; Flandre, Denis

doi:10.1109/esscir.2005.1541643

Cited by 15 publications

(6 citation statements)

References 7 publications

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“…This can place our design at the top of the state-of-the-art. The VCO in Reference [12] uses PD sal CMOS 0.13 urn process; it has no effect of the substrate loss by using high-resistivity sal substrates, this VCO shows interesting performances, in particularly the low power consumption but its FoM is roughly different from only 3.53 dB from that of our proposed design.…”

Section: Measurement Results and Discussionmentioning

confidence: 92%

5-GHz low phase noise CMOS LC-VCO with PGS inductor suitable for ultra-low power applications

Oualkadi

2009

2009 Mediterrannean Microwave Symposium (MMS)

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A fully integrated LC-VCO fabricated in 0.13 um CMOS technology is presented in this paper. The VCO achieves a wide tuning range of 31.43 % (from 3.841 GHz to 5.381 GHz). The measured phase noise is -120.63 dBclHz at 1 MHz offset from the carrier at 5.287 GHz. The current dissipation of the VCO is 1.32 mA from the 1.5 V power supply. The VCO figure of merit is greater than 190 placing this design among the top of the state-of-the-art.

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Section: Measurement Results and Discussionmentioning

confidence: 92%

5-GHz low phase noise CMOS LC-VCO with PGS inductor suitable for ultra-low power applications

Oualkadi

2009

2009 Mediterrannean Microwave Symposium (MMS)

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“…Several papers have reported efforts to create highquality inductors in HR-SOI processes since at least the early 2000s [1][2][3][4]. Q values reported vary from the range of 10 to 15, to as high as 30 or more, depending on the inductor's size, number of turns, frequency range, and the thickness of metals available.…”

Section: Previous Workmentioning

confidence: 99%

Loss mechanisms and quality factor improvement for inductors in high-resistivity SOI processes

Kuhn

2012

2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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Silicon-on-insulator processes have the potential to realize high-quality factors in spiral inductors, but only if the loss mechanisms involved are clearly understood. Partially-depleted SOI (PD-SOI) processes must address losses in the semiconducting Silicon layer below the spiral inductor turns, even when high-resistivity substrates are employed. These losses are illustrated with a simplified lumped-element model and an array of inductors with different materials below is measured to confirm the theory. Q values achieved are up to 19 in the popular frequency range of 1 to 6 GHz without the use of expensive thick-metal in the process.Index Terms -SOI, inductor, quality factor.

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“…Similarly, high-resistivity SOI wafers suffer from parasitic conduction at the substrate surface due to the presence of an inverted layer underneath the buried oxide (BOX) [16,19]. In [20], we investigated the effect of parasitic surface conduction in the case of different technologies, all relying on oxidized p-type HR bulk/SOI substrates.…”

Section: Transmission Linesmentioning

confidence: 99%

Wideband characterization of SOI materials and devices

Raskin

2007

Solid-State Electronics

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A low-power 5 GHz CMOS LC-VCO optimized for high-resistivity SOI substrates

Cited by 15 publications

References 7 publications

5-GHz low phase noise CMOS LC-VCO with PGS inductor suitable for ultra-low power applications

5-GHz low phase noise CMOS LC-VCO with PGS inductor suitable for ultra-low power applications

Loss mechanisms and quality factor improvement for inductors in high-resistivity SOI processes

Wideband characterization of SOI materials and devices

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