A low power 10‐bit 1 MS/s cyclic analog to digital converter for complementary metal oxide semiconductors image sensors with comparator‐based switched‐capacitor technique

Abstract

This paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 W of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance.