A low-power 0.7-V H.264 720p video decoder

Finchelstein, D.F.; Sze, Vivienne; Sinangil, Mahmut E.; Koken, Y.; Chandrakasan, Anantha P.

doi:10.1109/asscc.2008.4708756

Cited by 13 publications

(19 citation statements)

References 7 publications

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“…This is only acceptable in applications with relaxed timing constraints. Many ultra-low-voltage circuits have recently been demonstrated: microcontrollers for biomedical applications [25,33], for wireless sensor nodes as well as dedicated ASICs for communication [35] or image processing [15,30].…”

Section: Ultra-low Voltage Operationmentioning

confidence: 99%

Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags

et al. 2011

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An important challenge associated with the current massive deployment of Radio Frequency Identification solutions is to provide security to passive tags while meeting their micro Watt power budget. This can either be achieved by designing new lightweight ciphers, or by proposing advanced low-power implementations of standard ciphers. In this paper, we show that the AES algorithm can fit into this micro Watt power budget by combining ultralow-voltage implementations with a proper selection of the process flavor in a low-cost nanometer CMOS technology. Interestingly, this approach only requires slight modifications to the standard EDA tool flow, without incurring the engineering costs of architecture optimizations. In order to demonstrate this claim, we successfully designed and manufactured an AES coprocessor in a 65 nm low-power CMOS process. We prove with measurement results obtained from a set of 20 manufactured dies that the proposed coprocessor can be safely operated down to 0.32 V with an energy per 128-bit encryption/decryption at least 2.75× lower than in previously published low-power AES implementations.

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Section: Ultra-low Voltage Operationmentioning

confidence: 99%

Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags

et al. 2011

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“…Thus, the processing of each partition must be synchronized. Synchronization can be done using data driven first-in-first-out queues (FIFOs) between engines, similar to the ones used in [21] and [22] between processing units.…”

Section: A Syntax Element Partitions (Sep)mentioning

confidence: 99%

A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding

Sze

Chandrakasan

2012

IEEE J. Solid-State Circuits

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Abstract-Future video decoders will need to support high resolutions such as Quad Full HD (QFHD, 4096 2160) and fast frame rates (e.g., 120 fps). Many of these decoders will also reside in portable devices. Parallel processing can be used to increase the throughput for higher performance (i.e., processing speed), which can be traded-off for lower power with voltage scaling. The next generation standard called High Efficiency Video Coding (HEVC), which is being developed as a successor to H.264/AVC, not only seeks to improve the coding efficiency but also to account for implementation complexity and leverage parallelism to meet future power and performance demands. This paper presents a silicon prototype for a pre-standard algorithm developed for HEVC ("H.

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“…Thus, the processing of each partition must be synchronized. Synchronization can be done using data driven FIFOs between engines, similar to the ones used in [1] between processing units.…”

Section: Syntax Element Partitioningmentioning

confidence: 99%

“…Parallelism can be used to lower the clock rate and compensate for the speed reduction. This approach has shown to be extremely effective in reducing the power consumption of video decoding [1]. Higher throughput allows for greater voltage scaling and consequently energy savings.…”

Section: Introductionmentioning

confidence: 99%

A high throughput CABAC algorithm using syntax element partitioning

Sze

Chandrakasan

2009

2009 16th IEEE International Conference on Image Processing (ICIP)

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Enabling parallel processing is becoming increasingly necessary for video decoding as performance requirements continue to rise due to growing resolution and frame rate demands. It is important to address known bottlenecks in the video decoder such as entropy decoding, specifically the highly serial Context-based Adaptive Binary Arithmetic Coding (CABAC) algorithm. Concurrency must be enabled with minimal cost to coding efficiency, power, area and delay. This work proposes a new CABAC algorithm for the next generation standard in which binary symbols are grouped by syntax elements and assigned to different partitions which can be decoded in parallel. Furthermore, since the distribution of binary symbols changes with quantization, an adaptive binary symbol allocation scheme is proposed to maximize throughput. Application of this next generation CABAC algorithm on five 720p sequences shows a throughput increase of up to 3x can be achieved with negligible impact on coding efficiency (0.06% to 0.37%), which is a 2 to 4x reduction in coding penalty compared with H.264/AVC and entropy slices. Area cost is also reduced by 2x. This increased throughput can be traded-off for low power consumption in mobile applications.

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A low-power 0.7-V H.264 720p video decoder

Cited by 13 publications

References 7 publications

Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags

Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags

A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding

A high throughput CABAC algorithm using syntax element partitioning

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