A Low-Phase Noise ADPLL Based on a PRBS-Dithered DDS Enhancement Circuit

Abstract

This paper aims to design an all-digital phase-locked loop (ADPLL) intended for professional digital audio data conversion applications. The method used for designing is based on an analogy between analog PLL and ADPLL. Managing a low-jitter effect, a comparative study between discrete voltage-controlled oscillator (DVCO) and direct digital synthesis (DDS) based on a pseudorandom binary sequence (PRBS) generator is performed. The features of the design in this work are high-precision and low harmonic distortion DDS which is combined with ADPLL. For model-based design validation, a rapid register transfer level (RTL) with VHSIC hardware description language (VHDL) is practiced and the dynamic performance result indicates a significant improvement in total harmonic distortion (THD) ([Formula: see text][Formula: see text]dB) and a better resolution of 18.97[Formula: see text]bits for audio applications based on the aid of phase dithering DDS enhancement circuit.