A Low-Latency Pipelined 2D and 3D CORDIC Processors

CORDIC Architectures: A Survey

“…This remaining angle is chosen such that a first order Taylor series approximation of sin θ r and cos θ r , calling θ r the remaining angle, may be employed as sin θ r ≈ θ r and cos θ r ≈ 1. The architecture for the implementation of this algorithm using nonredundant arithmetic is presented in [49]. The iteration equations of this algorithm for the first n/2 + 1 microrotations are same as those for the conventional CORDIC algorithm (11).…”

“…The low latency nonredundant radix-2 CORDIC algorithm achieves constant scale factor since σ i ∈ {−1, 1} and performs the scale factor compensation concurrently with the computation of x and y coordinates, using two multipliers in parallel [49]. This is in contrast to two series multiplications required in the algorithm [50].…”

“…For the microrotations in the range i ≥ (n/6), the σ i values are predicted from the the remaining angle after the first n/6 [60]. Thus, the complexity of the w path is n/6, compared to n in the other architectures [42][43][44][45][46][47][48][49][50][51][52][53] presented in the previous sections. For the range 0 ≤ i < (n/6), microrotations are pipelined in two stages to increase the throughput.…”

“…Hence, we have compared all the CORDIC algorithms with respect to the latency required for the rotation computation, excluding the scale factor compensation and redundant to binary conversion stages. All the architectures presented in this table are implemented using redundant arithmetic except the conventional CORDIC [3] and the Low latency nonredundant CORDIC [49].…”

“…In [49], the x/ y coordinates are computed iteratively for the (n/2 + 1) iterations using (n/2 + 1) number of fast adders. These values are used to compute the final x/ y coordinates using two multipliers in parallel and one adder resulting in the latency of ((n/2 + 2)t adder + t multiplier ).…”