A low-latency GALS interface implementation

Chang, Yu‐Jung; Chen, Wei-Che; Tsai, Hung-Yue; Cheng, Wei-Min; Chen, Chang-Jiu; Cheng, Fu-Chiung

doi:10.1109/apccas.2010.5774997

Cited by 3 publications

(1 citation statement)

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“…The power intent diagram for 8051_RAM block is shown in Fig.10 with all power gating sequence control signals. The asynchronous wrappers for 8051_ALU and 8051_CTR along with local pausible clocking element was designed based on 4-phase handshaking communication protocol principles [27]. The STG, SG and corresponding equations for power gating sequence is generated using petrify.…”

Section: Implementation and Synthesis Flowmentioning

confidence: 99%

Synthesizing power gating sequence in pausible clock based GALS designs

Rajakumari¹,

Sharma²,

Kishore

et al. 2013

2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)

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with the improving evolution in VLSI technology most of the digital circuits are becoming SOCs. However most of the SOC systems are synchronous designs and the issues like clock skew, power consumption and EMI are related to clock network. Asynchronous circuits can offer benefits like reduced power and improved performance. However implementing whole design with asynchronous design style is a challenge due to lack of CAD tools. The GALS (Globally-Asynchronous LocallySynchronous) design methods brings compromise between synchronous and asynchronous design styles by separating each synchronous blocks in SoC with asynchronous interface. Each synchronous block in SoC can perform operation with its own local clock. The data communication among synchronous blocks can be achieved via handshaking signals after pausing the local clocks. Though these GALS system architectures ensures less dynamic power through clock less asynchronous interface the leakage power contribution to total power equation is still a challenge in deep submicron technologies. Power gating is most effective technique for synchronous design to address leakage power. In this paper an asynchronous power gating sequence generation is proposed for GALS synchronous blocks which has to wait long time for data. To corroborate the proposed technique a synthesis flow is proposed to implement asynchronous 8051 micro controller. The implementation was done using Synopsys SAED 90 nm libraries and the experimental results shows 30% leakage power reduction for power gating blocks.

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Section: Implementation and Synthesis Flowmentioning

confidence: 99%