A low jitter 2.125GHz serial link for optical transmission

Abstract

In this paper, a 2.125GBd 10bit Serialize/Deserialize (SERDES) system has been implemented, transmitter section and receiver section are capable of working simultaneously. A new architecture of CDR and PLL has been proposed. The same coarse loop is used in the PLL and CDR to set each digital control bits of VCO. And a pre-emphasis driver is utilized to compensate for the high frequency attenuation in channel. The measurement results show that SERDES has a RMS jitter of 28ps.