A Low Insertion-Loss 10–110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS

Ciocoveanu, Radu; Weigel, Robert; Hagelauer, Amelie; Issakov, Vadim

doi:10.1109/bcicts.2018.8550908

Cited by 7 publications

(3 citation statements)

References 10 publications

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“…WITCHES are among the most widely used components in RF and mm-wave systems. In the recent years, some wideband switches were introduced and they adopt inductors/transformers and transmission lines in order to achieve good performance over frequency [1][2][3][4][5], but with a negative impact as for the area on chip. Fully-depleted siliconon-insulator (FDSOI) with ultra-thin body and buried-oxide layer allows taking most of the advantage of SOI technology [5] and has been used to implement prior-art switches [1,3,4,[6][7][8].…”

Section: Introductionmentioning

confidence: 99%

A Compact DC-110GHz SPST Switch in 22nm FDSOI CMOS

Nhut

Zito

2023

IEEE Trans. Circuits Syst. II

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This brief reports a compact DC-110GHz single-pole single-throw (SPST) switch in 22nm FDSOI CMOS technology. The switch adopts solely three n-MOSFETs, two of them with a special device option to reduce the substrate parasitic effects, and a third n-MOSFET in parallel to the gate resistance of the series n-MOSFET to improve isolation. Unlike prior wideband mmwave switches, it does not make use of any large passive components, such as spiral inductors, transformers and transmission lines, which are prone to large parasitic effects, including losses, and require large area on silicon. Altogether, the novel switch circuit allows a very compact design, low losses and high isolation performance. The switch exhibits an insertion loss lower than 3.1 dB, an isolation better than 22 dB, and a return loss better than 12 dB, over the entire frequency range from DC to 110 GHz. The area on die amounts to 160 µm 2 , that is up two or more orders of magnitude smaller than prior wideband mm-wave SPST switches.

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Section: Introductionmentioning

confidence: 99%

A Compact DC-110GHz SPST Switch in 22nm FDSOI CMOS

Nhut

Zito

2023

IEEE Trans. Circuits Syst. II

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“…Working as most front-end parts of an RF communication system, the performance of the RF switch directly affects the performance of the entire communication system. A poorly functional switch can limit power amplifier operation and reduce receiver sensitivity 1 . Past studies have shown that switches based on GaAs/GaN are less integrated and more expensive 2,3 .…”

Section: Introductionmentioning

confidence: 99%

A low insertion loss RF switch using a 130 nm SOI process

Zhang¹,

Zheng

et al. 2022

J. Phys.: Conf. Ser.

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To realize a better radio frequency (RF) communication system, the RF switch, as an important module, is used to cooperate with other devices to form an RF front end for optimizing communication performances. This paper designs a single-pole multi-throw (SPMT) RF switch, which exhibits a low insertion loss of 0.57 dB at 1.9 GHz under the voltage of 2.2 to 4.7 V. The RF switch is fabricated using a 130 nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) process. It can be used in multi-frequency and multi-mode applications such as 4G/5G. The proposed RF switch has competitive performance and can be combined with other modules to achieve better wireless communication and promote the development of ultra-wideband and multi-mode wireless communication systems.

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“…To improve the power efficiency and sensitivity of transceivers, T/R switches require low insertion loss (IL) and high isolation to avoid RX being interfered by TX. [9][10][11][12] Hence, SPDT switches are key components in mm-wave phased array systems, and SPDT switch design is extremely challenging.…”

Section: Introductionmentioning

confidence: 99%

Design of high‐isolation and low‐loss single pole double throw switch based on the triple‐coupled transformer for ultra‐wideband phased array systems

Wang

Wang³

et al. 2021

Circuit Theory & Apps

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This paper proposes a single pole double throw (SPDT) switch based on the triple-coupled transformer. The triple-coupled transformer utilizes a novel structure with three stacked coupled inductors which are placed in nonconcentric positions to ensure the isolation of SPDT switch. The SPDT switch obtains additional optimization space to improve insertion loss performance under the premise of reassuring isolation. The equivalent circuit model is built to interpret the mechanism of the SPDT switch and transformer. The proposed switch is implemented with the 65-nm CMOS process, the simulated results show the isolation between input-to-output ports are better than 25 dB at 24-38 GHz. The proposed SPDT switch achieves a minimum insertion loss of 1.56 dB with compact chip size 625 Â 370 μm 2 (with PADs).

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A Low Insertion-Loss 10–110 GHz Digitally Tunable SPST Switch in 22 nm FD-SOI CMOS

Cited by 7 publications

References 10 publications

A Compact DC-110GHz SPST Switch in 22nm FDSOI CMOS

A Compact DC-110GHz SPST Switch in 22nm FDSOI CMOS

A low insertion loss RF switch using a 130 nm SOI process

Design of high‐isolation and low‐loss single pole double throw switch based on the triple‐coupled transformer for ultra‐wideband phased array systems

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