“…While the control voltage V ctrl and bulk-biased PMOS varactors comply with the nominal 1.8 V supply in the 180-nm complementary metal-oxide semiconductor (CMOS) process, which may be required by other analog circuitry. 20 As shown in Figure 3B, the conventional MOS varactors are placed between the two sets of PMOS varactors, M 3 /M 4 and M 5 /M 6 , in the proposed linearity-compensation network, with layout area of only 20% compared with that of the conventional bias-shifted compensation network which is shown in Figure 3A. Furthermore, the proposed linearitycompensation network can be paralleled with more sets of bulk-biased varactors to achieve better linearity without dealing with the layout constraint of the bias-shifted topology due to the large DC-blocking capacitance, for example, two sets of PMOS varactors in this design as opposed to only one set in Peng et al 4 Figure 4A shows the C-V curves of the three sets of varactors, with bulk voltage of M 5 -M 6 biased at 0.75 V and bulk voltage of M 3 -M 4 biased at 1.4 V. The combined C-V curve of the total capacitance of the LC tank versus the control voltage exhibits a wide linear range from 0.6 to 1.4 V. As shown in Figure 4B, compared with that of the bias-shifted topology, the quality factor of the proposed capacitor network in Figure 2B is almost the same in the linear control range.…”