A low damage RIE process for the fabrication of compound semiconductor based transistors with sub-100nm tungsten gates

Li, X.; Cao, Xiehong; Zhou, Haiping; Wilkinson, C.D.W.; Thoms, S.; Macintyre, D.; Holland, M.; Thayne, Iain

doi:10.1016/j.mee.2006.01.074

Cited by 9 publications

(4 citation statements)

References 7 publications

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“…Mass-manufacturing of micro/nanostructures on semiconductors is of great demand in ultralarge scale integration circuits (ULSI), optoelectronics, and photovoltaics devices, especially for III–V semiconductors (i.e., GaAs and InP) with high saturation electron velocity and high electron mobility . However, as for the micro/nanofabrication technologies for semiconductors, nanoimprint lithography and ultraprecision machining technology based on contact mode is more likely to result in surface damage because of the fragile surface. , Micro/nanofabrication technologies with noncontact modes, such as laser beam and focused ion beam writing always require high energy, which tends to alter surface components. , Based on the principles of electrochemically induced chemical etching, confined etchant layer technique (CELT) has proven to be an effective electrochemical micro/nanofabrication technique, with low cost, high throughput, and no need for a mask. − The noncontacting mode of operation and the mild chemical etching reaction minimize surface damage and thermal effects. Most importantly, a homogeneous reaction between etchant and scavenger is used to confine the etchant in a depleted layer with a thickness of nanometers, which ensures a nanoscale fabrication resolution. − …”

Section: Introductionmentioning

confidence: 99%

“…2,3 Micro/nanofabrication technologies with noncontact modes, such as laser beam and focused ion beam writing always require high energy, which tends to alter surface compo-nents. 4,5 Based on the principles of electrochemically induced chemical etching, confined etchant layer technique (CELT) has proven to be an effective electrochemical micro/nanofabrication technique, with low cost, high throughput, and no need for a mask. 6−14 The noncontacting mode of operation and the mild chemical etching reaction minimize surface damage and thermal effects.…”

Section: Introductionmentioning

confidence: 99%

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Tip–Substrate Distance-Dependent Etching Process of III–V Semiconductors Investigated by Scanning Electrochemical Microscopy

Zhang¹,

Sartin²,

Guo³

et al. 2019

J. Phys. Chem. C

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Based on the fundamentals of electrochemically induced chemical etching, the confined etchant layer technique (CELT) has proven to be a versatile electrochemical micro/nanofiabrication technique. However, the tip−substrate distancedependent etching reaction rate and surface passivation reaction rate make it difficult to correlate these electrochemical micro/ nanofabrication conditions with practical etching results. In this article, combining topography analysis of etching pits and finite element method (FEM), we investigated the effect of tip−substrate distance coupling with etching reaction kinetics (k e ) and passivation reaction kinetics (k p ) on the etching of III−V semiconductors. Further, the coupling relationships between tip− substrate distance and reaction kinetics are correlated to practical etching profiles. It is found that tip−substrate distance is more important for etching resolution, while k e and k p are more important for etching efficiency. For materials with small k p (i.e., n-GaAs), choosing a suitable etchant to ensure large k e and dynamically controlling the stepping motor to maintain nanoscale tip−substrate distance are crucial for achieving high etching resolution and efficiency. However, for materials with large k p (i.e., n-InP), choosing suitable complexing agents to ensure small k p and controlling a suitable tip−substrate distance to improve mass transport of products are crucial for achieving high efficiency. These guidelines will be instructive for both CELT and other electrochemical micromachining techniques.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Tip–Substrate Distance-Dependent Etching Process of III–V Semiconductors Investigated by Scanning Electrochemical Microscopy

Zhang¹,

Sartin²,

Guo³

et al. 2019

J. Phys. Chem. C

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“…A few non-traditional micromachining techniques were developed for this purpose, such as the energy-beam (e.g., electron, plasmon, laser, and so forth) direct writing and the ultra-precision cutting. However, these techniques usually cause residual stress as well as surface and sub-surface damage due to the violent energy release during the material removal processes. , …”

Section: Introductionmentioning

confidence: 99%

“…However, these techniques usually cause residual stress as well as surface and sub-surface damage due to the violent energy release during the material removal processes. 9,10 Free of tool wear, residual stress, and surface and sub-surface damage, electrochemical machining plays an irreplaceable role in the 3D-MNSs microfabrication. 11 In general, electrolyzing and electroforming apply to conductive materials.…”

Section: Introductionmentioning

confidence: 99%

Chemical Etching Processes at the Dynamic GaAs/Electrolyte Interface in the Electrochemical Direct-Writing Micromachining

Han

Wang

Sartin

et al. 2021

ACS Appl. Electron. Mater.

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Electrochemical fabrication of functional three-dimensional micro/nanostructures (3D-MNSs) at the wafer scale is important in the semiconductor industry, but it involves complex interfacial reactions. We demonstrated the use of scanning electrochemical microscopy (SECM), a competitive direct-writing micromachining technique, to achieve this by electrochemically induced chemical etching processes on semiconductor wafers. Besides the complex reaction kinetics, the machining accuracy is a function of various parameters, such as the SECM tip size, tip–substrate distance, etching time, the concentration of etchant precursors, and the coupling surface adsorption and passivation on the semiconductor wafer. Here, we investigated the influences of these factors on the machining profiles of etching pits and established a numerical model to predict and control the machining results. Based on the finite element analysis, the unexpected microbulges in the machining process are demonstrated to be caused by the insufficient mass transport and the precipitation of the etching product. The results are instructive for the controllable microfabrication of 3D-MNSs on the semiconductor wafers.

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Nanoscale Pattern Transfer

Cui

2008

Nanofabrication

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A low damage RIE process for the fabrication of compound semiconductor based transistors with sub-100nm tungsten gates

Cited by 9 publications

References 7 publications

Tip–Substrate Distance-Dependent Etching Process of III–V Semiconductors Investigated by Scanning Electrochemical Microscopy

Tip–Substrate Distance-Dependent Etching Process of III–V Semiconductors Investigated by Scanning Electrochemical Microscopy

Chemical Etching Processes at the Dynamic GaAs/Electrolyte Interface in the Electrochemical Direct-Writing Micromachining

Nanoscale Pattern Transfer

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