A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor

Abstract

This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA) and NIOS II microprocessor applying a C to Hardware (C2H) acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI) technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system.

On-Board Detection and Matching of Feature Points

“…The curve is generated below a threshold t which determined if two descriptors are matched. Given one image pair covering the same land coverages, the recall as shown in Equation (10) is the ratio of the number of the correctly matched points to the number of corresponding matched points: recall = #correct_matches/#correspondence (10) In practice, the number of corresponding points is determined by the overlapping of the points in the image pair. The 1-precision as shown in Equation (11) is the ratio of the total number of the falsely matched points to the sum of the number of the correctly matched points and the number of the falsely matched points:…”

“…Meanwhile, the parallel processing characteristic and the pipeline structure of FPGA allow data to be processed more quickly with a lower power consumption than a similar microprocessor implementation and/or CPU [5,6]. In addition, several FPGA-based implementations are proposed with soft cores microprocessors to realize the complex algorithms [7], such as, motion estimation algorithms [8][9][10] and epsilon quadratic sieve algorithm [11]. Hence, the FPGA-based implementation of detection and matching algorithms are widely researched.…”

On-Board Ortho-Rectification for Images Based on an FPGA

“…As described in part (2) of Section 2.2.2, to obtain the scanning coordinates, the affine transformation coefficients must be solved. To this end, four fiducial points for each study area are used to acquire the affine transformation coefficients according to Equation (16), and they are shown in Table 2. After the above necessary parameters are acquired, they are taken as the constants and input to the proposed FPGA-based ortho-rectification system.…”

“…In recent decades, the field programmable gate array (FPGA) has been widely used in the image processing (such as imaging compression [7,8], filtering [9][10][11], edge detection [12,13], real-time processing of video images [14,15], and motion estimation [16][17][18]) to make real-time processing come true. González et al [16,17] optimized matching-based motion estimation algorithms using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) and on-chip memory in Nios II processors, and presented a low-cost system. Botella et al [18] proposed an architecture for a neuromorphic robust optical flow based on FPGA, which was applied in a difficult environment.…”

Real-time motion estimation for image and video processing applications

“…The final aim of optical flow estimation is to compute an approximation to the motion field from timevarying image intensity. Several different real-time approaches to motion estimation have been proposed [1][2][3][4][5][6][7][8][9], and these could preliminarily be classified as belonging to matching domain approximations [10], energy models [11] and gradient models [12,13]. Despite the number of different models and algorithms [14], none of them covers all the problems associated with real-world processing, such as noise, illumination changes, second order motion, occlusions, etc.…”