A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC

Su, Ching-Lung; Yang, Wei-Sen; Chen, Yali; Yang, Yao-Chang; Chen, Ching-Wen; Guo, Jiun-In; Tseng, Shau-Yin

doi:10.1109/apccas.2006.342454

Cited by 6 publications

(1 citation statement)

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“…It performs block-matching algorithm between successive frames to determine a motion vector (MV) for each MB in the current frame, and then obtains the residual data to be compressed. First of all, we adopt our low complexity, high quality fast algorithms for H.264 IME and FME by reducing over 90% of complexity as compared to the full search ME algorithms adopted in JM9.7 [13,14]. The key operation, i.e.…”

Section: Motion Estimationmentioning

confidence: 99%

An embedded coherent-multithreading multimedia processor and its programming model

Chu

Chou

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Multithreading and multi-core processing have been shown to be powerful approaches for boosting a system performance by taking advantage of parallelism in applications. This paper presents a processor design by unifying RISC and multithreading DSP for the sophisticated multimedia applications with advanced standards such as H.264. The proposed design not only minimizes integration costs for embedded multithreading/multi-core design by independent coherent threads, but also reduces the memory bandwidth requirements by one-stop streaming buffer and a very fast data exchange mechanism. With the proposed techniques and appropriate programming model, we can achieve 78% reduction of memory bandwidth and 89% reduction of processing time in H.264 video encoding, compared to traditional single stream micro-processor.

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Section: Motion Estimationmentioning

confidence: 99%