A low-cell-stress SOI SRAM sensing technique

Abstract

One of the challenges experienced in the PDISOI CMOS technology development is the cell stability degradation caused by half selected cell disturb. Due to hysteretic body charge accumulation, high body voltage. and resultant low V! in the access transistor of the SRAM cell, the content of an unselected cell may be unintentionally overwritten when it is on the same local word line of a currently selected cell. As a technology solution. high V, implant can be applied to the array area at the expense of one additional masking step and performance degradation. Alternatively, the cross-coupled current mirror sensing scheme, with a lower bit line voltage. may be employed. However, more devices as well as multiple body contacts are required in order to realize precision parameter matching. Low-power SRAM techniques such as the charge transfer sense amplifier [l] can be yet another possible solution. In this paper, we present a low-cell-stress latch-type sensing system, which seeks to bias the bit lines low as frequently as possible to relieve voltage stress on the access transistor for improved cell stability and yield while maintaining high performance. This technique is desirable for low-power circuit applications.The prechargdequalization voltage for bit and data lines is set to a level. V , ,substantially lower than V , , to reduce excessive passgate leakage current affecting the storage node. Such a preventive, or remedial. measure improves array reliability in the PD/SOI technology. This technique features: (1) precharge voltage V , for complementary bit lines in read and dormant cycles; (2) precharge voltage Vx, for complementary data lines during the precharge phase of a read cycle: and (3) full rail voltage for complementary data lines after the onset of amplifier firing in a read cycle. Burdens on SO1 device design can thus be lightened by balancing leakage and performance. Fig. 1 shows the schematic diagram of this sensing system, which encompasses a cross-coupled latch topology with low-current pre-amplifying PFET elements activated before firing and full NFET/PFET amplifying elements activated upon firing. The PFET pre-amplification mechanism aids offset voltage development before the sense amplifier is fired, which sufficiently compensates the longer transition time needed for the slower side of data line to go from V , , to Vac. The ."I" side of the data line goes to V , after firing and only returns to the precharged state after passing of data to other parts of the circuit under normal Vdd. Data lines operate between Vac and ground during actual sensing to retain amplifier sensitivity and robustness. Power saving is achieved from reduced swings as a result of the lower precharge voltage. In a write cycle. selected bit lines undergo rail-to-rail operations, as are most performance beneficial. Other unselected cells on the same selected word line still have their bit lines precharged to V , .Hence, any unintentional write due to the half select condition can be avoided. This technique takes advantage of t...