A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit

Abstract

This paper presents a low area on-chip delay measurement system using an embedded delay measurement circuit. To reduce the area, the proposed method does not demand the measurement of the exact path under measurement, but the measurement of a path including the path under measurement and wires of clock tree unlike the conventional methods. The proposed Stop Signal Generator (SSG) consists of OR gate trees and a selector circuit. In addition, the area of SSG is lower than the conventional one. SSG is additional circuit which sends the transition from the output of the path under measurement to the embedded delay measurement circuit. Therefore, the area of the proposed system is lower. Because the area is low, the proposed method can be used for small-delay defect detection in manufacturing testing and failure prediction due to aging after shipment. We can apply the proposed delay measurement system to any embedded delay measurement circuit that measures the time difference between the two input signal transitions sent to the circuit. The evaluation shows that the area overhead is 16.54%. It is 6.62% smaller than the conventional method, and 8.41% larger than standard scan design.

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

“…This method is able to give a precise measurement. In addition, a method with smaller execution time and circuit area has been proposed [14]. Figure 1 shows the architecture of the on-chip path delay measurement method of [14].…”

“…However, the calibration is difficult. Some on-chip path delay time measurement methods using embedded delay measurement were proposed [9]- [14]. In these, delay times of paths are measured.…”

“…If a path delay time is beyond a specified time such as the three-sigma limit (users can set the specified time freely by taking into consideration the trade-off between yield and dependability), even if it is not beyond the system clock cycle, we regard it as a faulty path. Some previous works presented on-chip path delay time measurements based on this strategy [9]- [14]. By measuring delay time of the path under measurement (PUM), not only the gross and small-delay faults can be detected but also the amount of timing violation in the failing paths can be obtained under certain environment conditions [15], [16].…”

Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA

“…However, they are not detected by traditional manufacturing testing such as stuckat fault, transition and path delay fault testing. To detect small delay defects, some previous works presented testing using delay measurements for systems on a chip (SoCs) [2]- [4]. In these, path delay times are measured.…”

“…However, measurements using a variety of test clock frequencies take a long time because this measures a path many times changing test clock frequencies. The authors' group proposed a delay measurement using an embedded delay value measurement circuit (DVMC) [3], [4]. This measures a path delay time at one time, and thus a time required for measurements is shorter than that using a variety of test clock frequencies.…”