A Low-Area Fast-Lock Analog Delay-Locked Loop Using a Dual-Slope Technique for Multiphase Clock Generator

Lo, Yu-Lung; Chen, Pin-Tseng; Chan, Chia-Chen; Liu, Han‐Ying; 羅有龍,

doi:10.4156/aiss.vol4.issue18.11

AISS

2012

DOI: 10.4156/aiss.vol4.issue18.11

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A Low-Area Fast-Lock Analog Delay-Locked Loop Using a Dual-Slope Technique for Multiphase Clock Generator

Yu-Lung Lo¹,

Pin-Tseng Chen²,

Chia-Chen Chan³

et al.

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A Low-Area Fast-Lock Analog Delay-Locked Loop Using a Dual-Slope Technique for Multiphase Clock Generator

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