A Logic Fully Comparable Single-Supply Capacitor-Less 1-FinFET-1-Source-Channel-Drain-Diode (1T1D) Embedded DRAM MACRO in 16-nm FinFET

Hsieh, E. Ray; Huang, C. F.; Huang, S. Y.; Miu, M. L.; Lu, S. M.; Wu, Y. S.; Ye, Y. H.

doi:10.1109/lssc.2023.3311797

Cited by 3 publications

(1 citation statement)

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“…As a high-density alternative with inherent two-ported functionality, gain-cell embedded DRAM (GC-eDRAM) has become increasingly popular in recent years [33][34][35][36][37][38]. In addition to providing their 1R1W functionality, these memories provide a non-destructive read operation and low leakage power within a small silicon footprint.…”

Section: Introductionmentioning

confidence: 99%

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Golman,

Giterman,

Teman

2024

JLPEA

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Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability.

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