A Ka Band Power Amplifier with Varactor-Based Analog Predistortion in pMOS-SOI

Alluri, Sravya; Rostomyan, Narek; Leung, Vincent; Asbeck, P.M.

doi:10.1109/pawr53092.2022.9719848

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…A linearizer technique of cold-mode MOSFET [14][15][16][17][18][19][20] is implemented in the design. It not only improves the linearity of the design but also improves the gain at higher frequency bands.…”

Section: Proposed Designmentioning

confidence: 99%

“…In higher frequency bands, the circuits using digital predistortion technique consumes more power due to higher clock rates. Hence analog predistortion [14][15][16], which can be divided as active and passive, are seen as a better alternative. Passive analog predistortion is less complex compared to its active counterpart and does not obviously add any gain, however it does improve the linearity, and is considered as a better option for high-frequency applications [17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization

Quadir,

Jain,

Kashfi

et al. 2023

IET Circuits, Devices & Systems

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A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.

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