A Just-in-Time Customizable processor

Chen, Liang; Tarango, Joseph; Mitra, Tulika; Brisk, Philip

doi:10.1109/iccad.2013.6691166

Cited by 15 publications

(10 citation statements)

References 38 publications

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“…There are minor per-approach variations to these segments, for instance, maximum size (e.g., number of instructions) of the segment [19,77], presence of instructions unsupported by the accelerator [17,79], total number of inputs/outputs into the sequence [13,68], the type of stride [58] in the case of loops, or support for conditional execution, i.e., multiple paths [67].…”

Section: Types Of Binary Segmentsmentioning

confidence: 99%

“…In [5], Bansal et al present a performance analysis of mesh arrays as a function of FUs capabilities. Row designs prefer more specialized units supporting a reduced set of operations, especially if they are tightly integrated [13,17]. Some designs find a tradeoff, using mostly simple FUs together with a smaller number of more specalized units [67].…”

Section: Supported Operationsmentioning

confidence: 99%

“…Access E2, Exec. Model [13] present the JIT Customizable (JiTC) processor, which is based on a multistage Specialized Functional Unit (SFU). The SFU can be reconfigured in a per-cycle basis and was designed after analysis of 21 applications.…”

Section: Polymorphic Pipeline Arraymentioning

confidence: 99%

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Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

2020

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The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices.

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Section: Types Of Binary Segmentsmentioning

confidence: 99%

Section: Supported Operationsmentioning

confidence: 99%

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Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

2020

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“…The most well known include the DIM [2], the Warp processor [10], and the CCA [11]. Recent approaches include the work presented in [12] and the Dynamically Specialized Execution Resource (DySER) approach [3].…”

Section: Related Workmentioning

confidence: 99%

Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support

Paulino

Ferreira

Cardoso

2014

2014 IEEE International Symposium on Parallel and Distributed Processing With Applications

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This paper presents a binary acceleration approach based on extending a General Purpose Processor (GPP) with a Reconfigurable Processing Unit (RPU), both sharing an external data memory. In this approach repeating sequences of GPP instructions are migrated to the RPU. The RPU resources are selected and organized off-line using execution trace information. The RPU core is composed of Functional Units (FUs) that correspond to single CPU instructions. The FUs are arranged in stages of mutually independent operations. The RPU can enable several stages in tandem, depending on the data dependencies. External data memory accesses are handled by a configurable dual-port cache. A prototype implementation of the architecture on a Spartan-6 FPGA was validated with 12 benchmarks and achieved an overall geometric mean speedup of 1.91x.

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“…This approach was based on ILP model and relaxes designer from the data bandwidth which is usually limited by FSL channels. In the same context [9] used SFU (specialized functional units) in customized processor to support extension in parallel fashion.…”

Section: Fig 3: Synthesis Of the Customized Hardware And Software Commentioning

confidence: 99%

Instruction Customization: A Challenge in ASIP Realization

Shrimal¹,

Jain²

2014

IJCA

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An Application Specific Instruction set Processors (ASIP) or alternatively known as customized processor is a processor designed for a particular application or for a set of applications. Earlier surveys show that though a significant research has been done for this most promising processor design technology, still approaches used in them are lacking in methodologies to define processor configuration based on the requirements of the applications. There are number of approaches claiming to design and synthesize ASIPs but they are facing many challenges. This paper is an attempt to find major challenges faced by them as well as the current state of these promising techniques adopted by the industry. This paper also analyzed their effort to know really what they could have achieved so far and identified what should be done to make these techniques successful. If some limitations can be removed soon, these techniques are going to expand in an explosive manner.

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A Just-in-Time Customizable processor

Cited by 15 publications

References 38 publications

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support

Instruction Customization: A Challenge in ASIP Realization

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