A junctionless tunnel field effect transistor with low subthreshold slope

Ghosh, Bahniman; Bal, Punyasloka; Mondal, Partha Pratim

doi:10.1007/s10825-013-0450-2

Cited by 45 publications

(18 citation statements)

References 11 publications

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“…As a result, TFET device has attracted the attention of many researchers for digital applications [4,5]. However, the ultra-sharp doping concentration gradient in the source/channel and the drain/channel junctions complicates the fabrication process of TFET device in nanometer regime [6,7]. Recently, a junctionless TFET (JLTFET) has been proposed, in which issues caused by ultra-sharp doping concentration gradient in the source/channel and the drain/channel junctions are eliminated [6][7][8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

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Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Rajabi

Vadizadeh

2021

Int. J. Mod. Phys. B

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Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb vertical heterojunctionless tunneling field effect transistor (VHJL-TFET) has been suggested to optimize the digital benchmarking parameters. In the proposed VHJL-TFET with type II heterostructure (i.e., [Formula: see text] and [Formula: see text]), slight changes in gate voltage cause switching from OFF-state to ON-state. As a result, the electrical properties of Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET are excellent in the sub-threshold region. The heterostructure with III–V semiconductors in the source-channel region increases the ON-state current ([Formula: see text]) of the VHJL-TFET. Comparing the results of Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET with the simulated devices with type I heterostructure (i.e., [Formula: see text] and [Formula: see text]) and type III heterostructure (i.e., [Formula: see text] and [Formula: see text]) shows the improvement by 26% and 15% in the average subthreshold slope (SS). Sensitivity analysis for VHJL-TFET with the type II heterostructure shows that the sensitivity of OFF-state current ([Formula: see text] to the body thickness ([Formula: see text] and doping concentration ([Formula: see text] is more than the sensitivity of the other main electrical parameters. The Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET with a channel length of 20 nm, [Formula: see text] nm, and [Formula: see text] cm[Formula: see text] showed the [Formula: see text] mV/dec, [Formula: see text]/[Formula: see text], and [Formula: see text] mA/um. As a result, Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET can be a reasonable choice for digital applications.

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Section: Introductionmentioning

confidence: 99%

“…JLTFET is a heavy doped thin film semiconductor, in which the type and level of doping are unchanged throughout the device. In fact, in JLTFET device, the advantages of conventional TFET and junctionless field effect transistor are combined [7,13].…”

Section: Introductionmentioning

confidence: 99%

Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Rajabi

Vadizadeh

2021

Int. J. Mod. Phys. B

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“…To avoid complex fabrication processes and high thermal budgets in TFETs, the junctionless tunneling field effect transistor (JLTFET) [22][23][24][25][26][27][28][29][30] has been studied extensively in recent years, which uses uniformly high-doping concentration in the source, channel and drain regions so that the doping concentration and type of channel region are consistent with source region and drain region. Due to uniform doping, the JLTFET is immune to random dopant fluctuations (RDFs) and overcomes complex fabrication processes in manufacturing, meanwhile, source and drain region are formed by the charge plasma concept which further avoids high thermal budgets in the JLTFET.…”

Section: Introductionmentioning

confidence: 99%

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

et al. 2019

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This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

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“…Si-based Tunnel FET have the drawback of low ON state current due to large tunneling distance and high band gap. It is quite evident from the literature that, Tunnel FETs ON current enhancement can be achieved by increasing the electric filed across the junction, using low band gap materials, high-k dielectric material, junction less and silicon thin body [2][3][4][5][6][7][8][9][10][11][12]. The ON current enhancement in sandwiched tunnel barrier FET (STBFET) is comparable to the CMOS counterpart with improved sub-threshold slope and good output saturation mechanism which makes it a fairly good candidate for analog circuits [8].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Gate All Around Tunnel FET based Ring Oscillator Circuit

Dutta¹,

Soni²,

Pattanaik³

2019

IJRTE

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Abstract: In this work, we have designed and simulated a Gate All Around TFET (GAATFET) based 3 stage ring oscillator circuit and compared its performance with the CMOS based counterpart. The results of SPICE simulations indicate that GAATFET based ring oscillator circuit consumes 3.5 times lower power consumption in active mode than CMOS based ring oscillator. However, 0.43 ns and 0.17 ns of propagation delay is observed for GAATFET based ring oscillator and CMOS based ring oscillator circuit respectively. The obtained output waveform frequency for CMOS based ring oscillator is 2.5 times higher than the GAAATFET based ring oscillator. Further, undershoot is also investigated and it is found that the amplitude of undershoot in case of GAATFET based oscillator is roughly 6.5 times more as compared to CMOS based counterpart. The undershoot and delay observed in case of GAATFET based ring oscillator can be over-shaded by the fact that it has lower active power consumption than the CMOS based ring oscillator. Simulation results signify that GAATFET based ring oscillator can be deployed in future low power VLSI circuits and systems.

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A junctionless tunnel field effect transistor with low subthreshold slope

Cited by 45 publications

References 11 publications

Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

Design and Analysis of Gate All Around Tunnel FET based Ring Oscillator Circuit

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