A hybrid packet-circuit switched router for optical network on chip

Li, Hui; Gu, Huaxi; Yang, Yintang; Yu, Xiaoshan

doi:10.1016/j.compeleceng.2013.08.006

Cited by 10 publications

(5 citation statements)

References 25 publications

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“…In [18], Hui Li has combine the optical circuit switched and optical packet switched technique to cater for both traffic which are best effort and guaranteed service. The combination of both guaranteed traffic and best effort service makes it utilized the resources well and it has proven to increase the throughput and lower the delay but it require complex design for router architecture.…”

Section: B Problem On Low Resources Utilizationmentioning

confidence: 99%

A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC)

Razali

Othman

2015

2015 IEEE Student Conference on Research and Development (SCOReD)

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System-on-chip (SoC) architectures are getting communication-bound both from physical wiring and distributed computation point of view. Wiring delays are becoming dominating over gate delays, which favors short links. The larger SoC the more probably the overall computation is heterogeneous and localized rather than evenly balanced over the chip. These two factors motivate Network-on-Chip (NoC) that brings the techniques developed for macro-scale, multi-hop networks into a chip. But due to shrinkage of transistors and integration of billions of transistors in a single chip, has made NoC no longer suitable to cater for high latency and demand of bandwidth in a multicore processor environment. Thus they have introduce HONoC (hybrid optical network on chip) to cater for the high latency and demand in bandwidth. There are many research that focus on the area of architecture, routing algorithm and switching strategies in order to make the communication run optimally in HONoC. The purpose of this paper is to evaluate main problems in HONoC. From the evaluation, three main problems has been identified which are path collisions, low resource usage and high power consumption in HONoC

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Section: B Problem On Low Resources Utilizationmentioning

confidence: 99%

A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC)

Razali

Othman

2015

2015 IEEE Student Conference on Research and Development (SCOReD)

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“…The photonic switch consists of a 4x4 nonblocking Photonics switch, which is carefully composed of the photonic basic building blocks, including 1x2 and 2x2 photonic switching elements (PSE), micro-ring resonators (MRR), and waveguides [32]. An electronic router in Fig.6, is a basic store-and-forward packet-switched router [33]. It consists of three sub-modules working together, including router arbiter, router crossbar, and router in port.…”

Section: ) Processing Planementioning

confidence: 99%

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

et al. 2021

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Photonic networks and software-defined networks are two promising technologies to improve network-onchips performance, scalability, and resource utilization. Several architectures suffer from scaling limitations, high-power consumption, and noise interference drawbacks. In this paper, an enhanced photonic network-on-chip architecture called (SD-PNoC) is presented. The proposed architecture based on a hybrid hardware-software approach, and a Software-Defined Management Orchestrator (SDMO) to separate the network control and data forwarding planes. This orchestrator has hosted on the upper hardware router as a virtual layer capable of dynamic management. It reconfigures data forwarding paths and allows dynamic execution of different algorithms in real-time, as it scales the proposed topology based on both applications and the network requirements. The proposed SD-PNoC architecture, hierarchical communication protocols, and orchestrator management policies were implemented, simulated, and tested using a customized Phoenix-SIM framework in the OMNIT++ simulation environment. Numerous simulation experiments under different conditions have been performed and have proven that the performance of the proposed architecture is better than that of the conventional electronic network on chip (ENoC). Furthermore, simulation results without using the management policies showed that the latency is reduced by 46% and 25.5% for the 4x4 and 8x8 network structures, respectively. While the power consumption is reduced by 76.5% and 78.5% for the 4x4 and 8x8 network structures, respectively. Besides, the chip area is reduced by 33.4%. Moreover, simulation results of SDMO with using the management policies for the 8x8 network structures increased the enhancement of latency from 25.5% to 37.3% and the power consumption from 78.5% to approximately 80%, which assure the ability of the proposed architecture to remarkably enhance the overall performance of complex network-on-chip structures.

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“…However, simple solutions as 2D-meshes do not fulfill high-throughput low latency requirements. In this sense, some solutions as packet switching [8,9] or -the more disruptiveintroducing optical networks have been proposed. In this paper, we propose an orthogonal solution that reuses multiprocessor system snoopy concepts.…”

Section: Related Workmentioning

confidence: 99%

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the networkon-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-onchip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol -and hence its resources -, and moving this complexity to the network, leads to a global decrease in power consumption meanwhile area is barely affected. Benefits of our proposal are due to the high-throughput and low delay of the network, but also due to the simplicity of the coherence protocol. The proposed network and protocol minimizes communication amongst cores when compared to traditional solutions based either on 2D-mesh topologies or in directory-based protocols.

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A hybrid packet-circuit switched router for optical network on chip

Cited by 10 publications

References 25 publications

A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC)

A review on path collisions and resources usage in hybrid optical Network on Chip (HONoC)

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

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