A Hybrid Model of Turn-Off Loss and Turn-Off Time for Junction Temperature Extraction

Shao, Lingfeng; Xu, Guoqing; Li, Pengbo

doi:10.1109/jeds.2021.3125829

Cited by 11 publications

(2 citation statements)

References 22 publications

(38 reference statements)

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“…[10], on-resistance (R DS(on) ) [11], collector-emitter saturated voltage (V CE(sat) ) [4,12,13], drain-source current (I D ) [14], short circuit current (I SC ) [15], junction temperature (T j ) [16], thermal resistance from junction to case (R th ) [17], and others. From a practical point of view, the switching duration of the MOSFET is in the nanosecond-level or microsecond-level range, so accurately identifying the changes of degradation precursors caused by device degradation is difficult.…”

Section: Introductionmentioning

confidence: 99%

Failure quantitative assessment approach to MOSFET power device by detecting parasitic parameters

Yun

Yang

et al. 2022

Front. Phys.

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With the emerging wide bandgap (WBG) semiconductor development, the increasing power density and efficiency of power electronic converters may cause more switching oscillation, electromagnetic interference noise, and additional power loss, further increasing the probability of device failure. Therefore, determining and quantifying the failure of a metal-oxide-semiconductor-field-effect transistor (MOSFET), which assembled using WBG semiconductor in some applications, is crucial to improving the reliability of a power converter. This study proposes a novel failure quantitative assessment approach based on MOSFET parasitic parameters. According to the two-port network theory, MOSFET is equivalent to some second-order RLC circuits composed of independent inductances, capacitances, and resistances in series. Then, the frequency-domain impedance associated with the physical failure of MOSFET is identified through frequency domain reflectometry. Accelerated aging and bond wires cut-off experiments are employed to obtain various quality states of the MOSFET device. Result shows that the MOSFET quality level and its number of bond wire lift-offs can be quantified effectively. Drain-to-source on-resistance (RDS(on)) that normally represents the MOSFET quality shows a positive linear function relationship on drain-to-source parasitic resistance (RD + RS) during the quality degradation proceeding. This finding matches with the correlation established between RDS (on) and RD + RS in theory. Meanwhile, source parasitic inductance (LS) increases with the severity of bond wires faults, and even the slight fault shows a high sensitivity. The proposed approach would be an effective quality screening technology for power semiconductor devices without power on treatment, which can effectively avoid the impact of junction temperature and test conditions (current and voltage) on test results, and does not need to design additional test circuits. The test frequency range we used in this approach was 10–300 MHz, which to some extent is suitable for providing an on-line quality monitoring technology for high-frequency WBG power devices manufacturing.

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Section: Introductionmentioning

confidence: 99%

Failure quantitative assessment approach to MOSFET power device by detecting parasitic parameters

Yun

Yang

et al. 2022

Front. Phys.

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“…Therefore, it is important to accurately predict the junction temperature of IGBT to improve its reliability. In past studies, the temperature-sensitive parameter (TSP) method was often used to obtain the junction temperature of IGBTs [16,17]. This approach is often based on artificial intelligence algorithms [18,19].…”

Section: Introductionmentioning

confidence: 99%

Junction Temperature Prediction of Insulated-Gate Bipolar Transistors in Wind Power Systems Based on an Improved Honey Badger Algorithm

et al. 2022

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To reduce carbon dioxide emissions, wind power generation is receiving more attention. The conversion of wind energy into electricity requires frequent use of insulated-gate bipolar transistors (IGBTs). Therefore, it is important to improve their reliability. This study proposed a method to predict the junction temperature of IGBTs, which helps to improve their reliability. Limited by the bad working environment, the physical temperature measurement method proposed by previous research is difficult to apply. Therefore, a junction temperature prediction method based on an extreme learning machine optimized by an improved honey badger algorithm was proposed in this study. First, the data of junction temperature were obtained by the electro-heat coupling model method. Then, the accuracy of the proposed method was verified with the data. The results show that the average absolute error of the proposed method is 0.0303 °C, which is 10.62%, 11.14%, 91.67%, and 95.54% lower than that of the extreme learning machine optimized by a honey badger algorithm, extreme learning machine optimized by a seagull optimization algorithm, extreme learning machine, and back propagation neural network model. Therefore, compared with other models, the proposed method in this paper has higher prediction accuracy.

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Analysis of Probe Influences on TSEP Measurement Fidelity of Fast Switching SiC MOSFETs

Chen

Jia

Tan

et al. 2023

Lecture Notes in Electrical Engineering

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A Hybrid Model of Turn-Off Loss and Turn-Off Time for Junction Temperature Extraction

Cited by 11 publications

References 22 publications

Failure quantitative assessment approach to MOSFET power device by detecting parasitic parameters

Failure quantitative assessment approach to MOSFET power device by detecting parasitic parameters

Junction Temperature Prediction of Insulated-Gate Bipolar Transistors in Wind Power Systems Based on an Improved Honey Badger Algorithm

Analysis of Probe Influences on TSEP Measurement Fidelity of Fast Switching SiC MOSFETs

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