A hybrid frequency/phase-locked loop for versatile clock generation with wide reference frequency range

Lv, Sitao; Xu, Ni; Rhee, Woogeun; Wang, Zhihua

doi:10.1109/vlsi-dat.2016.7482533

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2016

DOI: 10.1109/vlsi-dat.2016.7482533

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A hybrid frequency/phase-locked loop for versatile clock generation with wide reference frequency range

Sitao Lv

Ni Xu

Woogeun Rhee

et al.

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A hybrid frequency/phase-locked loop for versatile clock generation with wide reference frequency range

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References 4 publications

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