2013 IEEE Aerospace Conference 2013
DOI: 10.1109/aero.2013.6496977
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A hybrid FPGA/Tilera compute element for autonomous hazard detection and navigation

Abstract: To increase safety for future missions landing on other planetary or lunar bodies, the Autonomous Landing and Hazard Avoidance Technology (ALHA T) program is developing an integrated sensor for autonomous surface analysis and hazard determination. The ALHAT Hazard Detection System (HDS) consists of a Flash LIDAR for measuring the topography of the landing site, a gimbal to scan across the terrain, and an Inertial Measurement Unit (IMU), along with terrain analysis algorithms to identify the landing site and th… Show more

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Cited by 17 publications
(8 citation statements)
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References 11 publications
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“…It is clear that, given the low amount of resources required by SA-FEMIP, fault tolerance techniques can be freely implemented within the selected device. Moreover, even after the implementation of fault tolerance techniques, space is also available to integrate, in the same device, additional FPGA-based IP-cores useful to accelerate other computationally intensive tasks performed during the descending phase (e.g., Hazard map computation [39]). This is very important considering the limited resources available in space applications.…”
Section: Resultsmentioning
confidence: 99%
“…It is clear that, given the low amount of resources required by SA-FEMIP, fault tolerance techniques can be freely implemented within the selected device. Moreover, even after the implementation of fault tolerance techniques, space is also available to integrate, in the same device, additional FPGA-based IP-cores useful to accelerate other computationally intensive tasks performed during the descending phase (e.g., Hazard map computation [39]). This is very important considering the limited resources available in space applications.…”
Section: Resultsmentioning
confidence: 99%
“…The HDS CE combines a Xilinx FPGA (surrogate for the path-to-flight Virtex-5 FPGA) and a multicore Tilera Tile-64 multicore processor (chosen for its common architecture with the Maestro processor developed under the Opera program 8 ), linked through a high-speed, 10 Gb/s XAUI connection. 9 The FPGA provides a precise hardware-based time stamp for all sensor data, and a time synchronization mechanism between the HDS and HV via an analog PPS pulse. The CE contains an optional data logger and console system (DLC).…”
Section: Hazard Detection System Architecturementioning
confidence: 99%
“…18 The HDS uses a flash lidar built by LaRC that is a compact, real-time, aircooled, 20 Hz TOF sensor system based on 3-D imaging camera technology developed by Advanced Scientific Concepts (ASC). 19 The LaRC lidar integrates a 1.064 μm class IV laser, 1 • field of view (FOV) f/7.3 receiver optics, 1 • divergence transmitter optics, and a 128 pixel × 128 pixel focal plane array (FPA) which resides in the ASC camera.…”
Section: Alhat Sensors and Vehicle Integrationmentioning
confidence: 99%