A hybrid design approach of PVT tolerant, power efficient ring VCO

Maiti, Madhusudan; Saw, Suraj Kumar; Mondal, Abir J.; Majumder, Alak

doi:10.1016/j.asej.2019.10.009

Cited by 10 publications

(4 citation statements)

References 30 publications

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“…x phl1 and x plh1 is the delay for high to low and low to high transition respectively. During high to low transition x 2 − x 1 and x 3 − x 2 is expressed in ( 9) and (10). By adding ( 9) and (10) high to low and low to high transition delay expressed in ( 12) and ( 13) respectively.…”

Section: Calculation Of Delay In Cs With Active Loadmentioning

confidence: 99%

“…During high to low transition x 2 − x 1 and x 3 − x 2 is expressed in ( 9) and (10). By adding ( 9) and (10) high to low and low to high transition delay expressed in ( 12) and ( 13) respectively. The ( 12) and ( 13) in (8) we get total delay of common source with active load inverter.…”

Section: Calculation Of Delay In Cs With Active Loadmentioning

confidence: 99%

“…A novel ring oscillator topology is designed by Li et al [9] measures high frequency of oscillation and high tuning range but consumes high power. Maiti et al [10] developed a hybrid power efficient ring VCO giving penalty of lower frequency of oscillation and low tuning range. In [11] authors developed a ring oscillator based on the current source this design consumes less power but lacks in frequency tuning.…”

Section: Introductionmentioning

confidence: 99%

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Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillator

Chavan

Aradhya

2023

IJECE

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<p><span lang="EN-US">The objective of the proposed work is to demonstrate the use of a hybrid approach for the design of a voltage-controlled oscillator (VCO) which can lead to higher performance. The performance is improved in terms of the tuning range, frequency of oscillation, voltage swing, and power consumption. The proposed hybrid VCO is designed using an active load common source amplifier and current starved inverter that are cascaded alternatively to achieve low power consumption. The proposed VCO achieves a measured phase noise of -74 dBc/Hz and a figure of merit (FOM) of -152.6 dBc/Hz at a 1 MHz offset when running at 5.1 GHz frequency. The hybrid current starved-current starved VCO (CS-CS VCO) consumes a power of 289 µW using a 1.8 V supply and attains a wide tuning range of 96.98%. Hybrid VCO is designed using 0.09 µm complementary metal–oxide–semiconductor (CMOS) technology. To justify the robustness, reliability, and scalability of the circuit different corner analysis is performed through 500 runs of Monte-Carlo simulation.</span></p>

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Section: Calculation Of Delay In Cs With Active Loadmentioning

confidence: 99%

Section: Calculation Of Delay In Cs With Active Loadmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillator

Chavan

Aradhya

2023

IJECE

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“…A new method of differential VCO achieves wider frequency tuning range, but suffers from maximum power consumption and high phase noise [23]. A new design of oscillator with process, voltage and temperature tolerant circuit achieves goof frequency of oscillation but it has very less FOM [24]. In the differential CSVCO circuit, achieves better oscillation frequency but suffers from maximum leakage power [25], [26].…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

Madheswaran,

Panneerselvam

2024

IJECE

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This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09%. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application.

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A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Jooq

Bozorgmehr

Mirzakuchaki

2020

Circuit Theory & Apps

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SummaryOver the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm2 physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.

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A hybrid design approach of PVT tolerant, power efficient ring VCO

Cited by 10 publications

References 30 publications

Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillator

Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillator

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

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