A hybrid algorithm for test point selection for scan-based BIST

Abstract

We propose a new algorithm for test point selection for scan-based BIST. The new algorithm combines the advantages of both explicit-testability-calculation and gradient techniques. The test point selection is guided by a cost function which is partially based on explicit testability recalculation and partially on gradients. With an event-driven mechanism, it can quickly identify a set of nodes whose testability need to be recalculated due to a test point, and then use gradients to estimate the impact of the rest of the circuit. In addition, by incorporating timing information into the cost function, timing penalty caused by test points can be easily avoided. We present the results to illustrate that high fault coverages for both area-and timing-driven test point insertions can be obtained with a small number of test points. The results also indicate a signi cant reduction of computational complexity while the qualities are similar to the explicitly-testability-calculation method.

Improving the test quality for scan-based BIST using a general test application scheme

“…Moreover, the target Although using the proposed MTS scheme increases the fault coverage, it may still require other DFT techniques to obtain a desired level of fault coverage. Therefore, we combine the proposed approach with a test point selection algorithm [16] to study the effects of using MTS on the required number of test points. Test points are added to circuits which have fault coverages lower than 98% with STS.…”

TPI for improving PR fault coverage of Boolean and three-state circuits

“…For each TP candidate, an event-driven mechanism is used to calculate the impact of the TP candidate on the global cost. This mechanism is illustrated in Figure 3 and is briefly described below; a more thorough description can be found in [13].…”

“…TPI algorithms for improving PR fault coverage with BIST can be found in [6,7,8,11,12,13,15]. Several of these TPI algorithms [7,13,15] use the testability analysis (TA) method COP [1] to find the best TP positions. COP can be used to estimate the probability that a fault will be covered by a PR pattern and hence determine which faults are RPR.…”

“…COP assumes that the circuit is combinational and that all flip-flops (FFs) are scan-able. Results of the HCRF TPI method of Tsai [13], a COP based TPI algorithm, have shown that the PR fault coverage of a circuit can be increased significantly with a relative small number of TPs.…”

“…Section 3 describes how COP, including COP for three-state circuits, is used in the HCRF TPI algorithm. The original HCRF TPI algorithm of Tsai [13] uses a cost function based on the COP measures to find the best TP positions; the TP candidates that reduces this cost function the most, are the TPs that will be inserted. Section 3 introduces our proposed cost function with which even better fault coverage improvements can be achieved.…”