A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation

Abstract

The optimization of receiver analog circuitry in modern high-speed input/output (HSIO) links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose an innovative objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-Si validation time.

Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks

“…The measurement system is based in the system margin validation (SMV) process [4], [38], which is a methodology to verify the signal integrity of a circuit board and assess how much margin is in the design relative to silicon characteristics and processes. The SMV methodology consists of measuring the Rx functional eye width and eye height by using on-die design for test (DFT) features until the eye opening has been shrunk to a point where the Rx detects errors or the system fails [6].…”

“…Tunable elements are proposed to adjust the analog circuit performance after chip fabrication [2], [3]. These tunable elements provide a way to reconfigure high-speed input/output (HSIO) links in post-silicon servers to mitigate the effects of system channels' variability [4], as illustrated in Fig. 1.…”

“…Post-silicon tuning requires first to measure the circuit performance and then determine the optimal knobs set based on measurement results. Current industrial practices for postsilicon tuning in HSIO links are very time consuming since they are typically based on exhaustive testing requiring massive lab measurements [4], resulting in an extremely high cost. Therefore, the challenge is how to make the post-silicon circuit tuning inexpensive by significantly reducing the number of lab measurements.…”

“…A method to do transmitter (Tx) equalization based on eye diagram analysis and direct optimization is proposed in [1]. In contrast, the problem of receiver (Rx) equalization is addressed in [4] by doing surrogate-based optimization using Kriging modeling. An extension of [4] is presented in [6] by developing several surrogate models to choose the most accurate one at the expense of increasing data collection time on the real system, and then perform numerical optimization of the PHY tuning Rx equalizer settings for a SATA Gen 3 channel topology.…”

Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

“…On the other hand, postsilicon tuning has been widely adopted to confront the silicon process variation. Tunable elements are proposed to adjust the analog circuit performance after chip fabrication [4], [5], allowing to reconfigure I/O links to cancel the effects of system channels' variability [6]. PHY tuning settings include: parameters of an equalizer at the Tx, Rx, or both; the clock and data recovery circuit settings; variable gain amplifiers; baud-spaced FFE in the Tx, and the bias voltages or currents values, among others [7].…”