SUMMARYIn the standard architecture of synchronisation network, chains of slave clocks (namely, stand-alone synchronisation equipment, SASE, and SDH equipment clock, SEC) transfer timing along synchronisation trails. Hence, the need to assess precisely the performance of timing transfer along such chains, not only in stationary conditions, but also under transient rearrangements occurring after input phase and frequency hits, due for example to reference switching. If possible, system analysis should be carried out beyond the usual assumption of linear behaviour, which is rather restrictive holding only for small perturbations on the input.In literature, very few papers analysed chains of slave clocks. In this work, the non-linear transient behaviour of SEC and SASE clock chains has been simulated in the time domain, in order to evaluate their timing rearrangements after non-small phase and frequency hits on the reference signal. Both homogeneous and non-homogeneous chains of SEC and SASE clocks have been studied in various configurations, assuming the classic analogue PLL scheme, in order to provide a useful and comprehensive survey, both in qualitative and quantitative terms, on the timing performance achievable when planning synchronisation trails of various type and length in a synchronisation network.