A Highly Sensitive Graphene-based Field Effect Transistor for the Detection of Myoglobin

Krsihna, B. Vamsi; Gangadhar, A.; Ravi, Sai Kishore; Mohan, D.; Panigrahy, Asisa Kumar; Rajeswari, V.; Matta, Durga Prakash

doi:10.1007/s12633-022-01790-9

Cited by 14 publications

(7 citation statements)

References 25 publications

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“…The and subthreshold swing (SS) are used to measure how well a device performs in the subthreshold range. The DIBL and SS are calculated using the given formulas [23]. The simulated device's SS and DIBL are calculated based on the following factors.…”

Section: Resultsmentioning

confidence: 99%

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

Siva Kumar,

Mohanraj

2024

IJRES

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<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

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Section: Resultsmentioning

confidence: 99%

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

Siva Kumar,

Mohanraj

2024

IJRES

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“…Figure 1 depicts a cross-sectional view of NsFET, which was created using Cogenda EDA tool. Many researchers have explored to use FET for various applications [22][23][24][25][26][27][28][29][30][31]. Channel length 10 nm with Fin dimension of 10 nm along with two fin's taken for the current study.…”

Section: Methodsmentioning

confidence: 99%

Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications

Kumar

Kumar²,

Vijayalakshmi³

et al. 2023

Journal of Nanomaterials

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Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, according to the proposed silicon-based NsFET. For low-power and high-switching applications, the results were verified and achieved quite well. When an NS width increases, although, the threshold voltage (Vth) tends to fall, resulting in a loss in subthreshold effectiveness. Furthermore, the proposed device performance, like subthreshold swing ION/IOFF, was studied with a conventional 2D FET. Hence, the proposed NsFET can be a frontrunner for ultra-low power and high-speed switching applications.

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“…Stacking liner arrangement and one-liner construction separated TSVs. Researchers looked examined BCB, Teflon, SiO2, Cu, and Polysilicon to see whether they might inhibit electrical involvement [23]- [25].…”

Section: Literature Studymentioning

confidence: 99%

Electrical signal interference minimization using appropriate core material for 3D integrate circuit at high frequency applications

Kumar,

Mohanraj

2024

IJECE

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As demand for smaller, quicker, and more powerful devices rises, Moore's law is strictly followed. The industry has worked hard to make little devices that boost productivity. The goal is to optimize device density. Scientists are reducing connection delays to improve circuit performance. This helped them understand three-dimensional integrated circuit (3D IC) concepts, which stack active devices and create vertical connections to diminish latency and lower interconnects. Electrical involvement is a big worry with 3D integrates circuits. Researchers have developed and tested through silicon via (TSV) and substrates to decrease electrical wave involvement. This study illustrates a novel noise coupling reduction method using several electrical involvement models. A 22% drop in electrical involvement from wave-carrying to victim TSVs introduces this new paradigm and improves system performance even at higher THz frequencies.

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A Highly Sensitive Graphene-based Field Effect Transistor for the Detection of Myoglobin

Cited by 14 publications

References 25 publications

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications

Electrical signal interference minimization using appropriate core material for 3D integrate circuit at high frequency applications

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