A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$  ADC With an Efficient Phase Quantization Noise Extraction Technique

Maghami, Hamidreza; Payandehnia, Pedram; Mirzaie, Hossein; Zanbaghi, Ramin; Zareie, Hossein; Goins, Justin B.; Dey, Siladitya; Mayaram, K.; Fiez, T.S.

doi:10.1109/jssc.2019.2954764

Cited by 26 publications

(10 citation statements)

References 19 publications

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“…Also, the idea to increase the order of quantization noise shaping of VCO-based ADCs by cascading multiple units in a MASH structure has been around for some time [30]- [33]. Successful silicon implementations have been presented recently, such as a 1-1 cascade with second-order quantization noise shaping (2 MHz bandwidth, 80dB SNDR) in [34]. On the other side of the spectrum, for sensing applications with low bandwidth but high resolution, [35] has presented a 1-1 sturdy-MASH architecture with the second loop and its integrator built entirely in digital circuitry, achieving second-order noise shaping and 16.1 bits of resolution.…”

Section: A Architectures For Reducing Quantization Noisementioning

confidence: 99%

“…In the near MHz range up to around 40 MHz, several efficient designs have been proposed. Here, a much wider variety of the techniques discussed above has been deployed successfully: some designs use analog techniques such as closed-loop operation [8], [9], [34] or input feedforward [19], whereas others use digital calibration to obtain adequate linearity [10]. Also higher-order noise shaping structures have successfully been demonstrated, like a 1+1 MASH structure in [34] or a third-order structure in [10].…”

Section: Bird's Eye Overview Of the State Of The Artmentioning

confidence: 99%

See 1 more Smart Citation

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS?Part 2: Architectures and Circuits

Gielen

Hernández

Rombouts

2020

IEEE Solid-State Circuits Mag.

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Section: A Architectures For Reducing Quantization Noisementioning

confidence: 99%

Section: Bird's Eye Overview Of the State Of The Artmentioning

confidence: 99%

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS?Part 2: Architectures and Circuits

Gielen

Hernández

Rombouts

2020

IEEE Solid-State Circuits Mag.

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“…An alternative to realizing a high-order VCO-based † ADC is to use a Multi-stAge noise-SHaping (MASH) structure. Maghami et al [21] realized secondorder noise shaping using a 1-1 MASH VCO-based ADC with two VCO-based † ADCs. As shown in Fig.…”

Section: Close-loop † † † Adcmentioning

confidence: 99%

A survey of voltage-controlled-oscillator-based ΔΣ ADCs

Zhong

Sun

2022

Tsinghua Sci. Technol.

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The benefits of technology scaling have fueled interest in realizing time-domain oversampling ( †) of Analog-to-Digital Converters (ADCs). Voltage-Controlled Oscillators (VCO) are increasingly used to design † ADCs because of their simplicity, high digitization, and low-voltage tolerance, making them a promising candidate to replace the classical Operational Transconductance Amplifier (OTA) in † ADC design. This work aims to provide a summary of the fully VCO-based † ADCs that are highly digital and scaling-friendly. This work presents a review of first-order and high-order VCO-based † ADCs with several techniques and architectures to mitigate the nonidealities introduced by VCO, achieving outstanding power efficiency. The contributions and drawbacks of these techniques and architectures are also discussed.

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“…This stems from the fact that VCOs offer highly digital, energyefficient, and scalable solutions [8]. Also, they realize relatively simple configurations of multi-bit noise shaping in A/D conversion or quantizer in delta-sigma modulator [9], [10]. Fig.…”

Section: Introductionmentioning

confidence: 99%

A Low-Phase-Noise CMOS Ring Voltage-Controlled Oscillator Intended for Time-Based Sensor Interfaces

2022

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We describe in this paper an improved ring voltage-controlled oscillator (VCO) showing a reduced phase noise while allowing an extended frequency tuning range. The phase noise improvement is obtained through the minimized contribution of tuning line noise while maintaining a rail-to-rail swing. The proposed VCO features a linear tuning characteristic yielding a constant gain over a wide range of operating frequencies. An analytical model is extracted resulting in closed-form expressions for the VCO phase noise. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The VCO prototype was fabricated in a 0.35 µm CMOS process. It consumes 0.903 mW from a 3.3 V supply when running at its maximum oscillation frequency of 9.37 MHz. The measured VCO phase noise is -147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the circuit occupies a silicon area of 0.005 mm 2 . A state-variable Matlab ® model of a timebased sensor interface has been developed including the impact of phase noise nonideality. The system-level simulations demonstrate that the PLL-based sensor interface exploiting the proposed VCO characteristics can achieve a 88.43 dB signal-to-noise ratio over a 1-kHz bandwidth.

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A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique

Cited by 26 publications

References 19 publications

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS?Part 2: Architectures and Circuits

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS?Part 2: Architectures and Circuits

A survey of voltage-controlled-oscillator-based ΔΣ ADCs

A Low-Phase-Noise CMOS Ring Voltage-Controlled Oscillator Intended for Time-Based Sensor Interfaces

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