A Highly Linear FPGA-Based TDC and a Low-Power Multichannel Readout ASIC With a Shared SAR ADC for SiPM Detectors

Tang, Yuxuan; Townsend, Todd; Deng, Hao; Liu, Yaqiang; Zhang, Runxi; Chen, Jinghong

doi:10.1109/tns.2021.3096162

Cited by 10 publications

(2 citation statements)

References 26 publications

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“…The reported power consumption was 23 mW (single channel). Another alternative to reduce the bin size in FPGAs (as well as in ASICs) is to combine the information from multiple TDLs, leading to a stochastic TDC [12,13]. In this technique, the bin size scales down with √ N TDL , while the power consumption almost scales by N TDL .…”

Section: State-of-the-art Tdcsmentioning

confidence: 99%

MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

et al. 2021

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This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2. The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption.

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Section: State-of-the-art Tdcsmentioning

confidence: 99%

MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

et al. 2021

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“…There are three commonly used approaches to implement high-performance FPGA-TDC: (1) multiphase method, which uses phase differences between multiple clocks as the interpolation mechanism to achieve high resolution [ 10 , 11 ]; (2) Vernier method, in which the resolution is given by the difference between two delay lines [ 12 ]; and (3) the tapped delay line (TDL) method, which uses FPGA’s cells as the interpolator to improve the resolution. In the past few years, TDL has become the main implementation method of FPGA-TDC [ 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 ]. In 2006, Song et al used dedicated carry chain as TDL for time interpolation, achieving a TDC with 69.5 ps resolution and 65.8 ps precision in the Virtex-II FPGA [ 18 ].…”

Section: Introductionmentioning

confidence: 99%

A Low Temperature Coefficient Time-to-Digital Converter with 1.3 ps Resolution Implemented in a 28 nm FPGA

Mao

Fang

Shi

et al. 2022

Sensors

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Time-to-digital converter (TDC) is the key technology to realize accurate time delay measurement in high-precision optical fiber time-frequency transmission and synchronization, optical sensing and many scientific applications. The performance of FPGA-TDC based on the carry chain is sensitive to the operating temperature. This paper presents a parallel multichain cross segmentation method, without multitime measurements, which merges multichain into an equivalent chain, achieving low temperature coefficient and maintaining high precision. The equivalent chain breaks the limit of the intrinsic cell delay of a single carry chain, improves the precision and reduces the impact of temperature variation significantly. A two-channel TDC based on parallel multichain cross segmentation method is implemented in a 28 nm fabrication process Kintex-7 FPGA. The results show that the performance of TDC is improved with the increase of the number of chains. The 10-chain TDC with 1.3 ps resolution, 4.6 ps single-shot precision performs much better than the plain TDC with 11.4 ps resolution, 8.7 ps single-shot precision. The resolution is stable with 0.0002 ps/°C temperature coefficient under an operating temperature range from 25 °C to 70 °C. Moreover, the proposed method reduces the complexity of the circuit and the resource usage.

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