A highly integrated GPS receiver for cellular handset

Abstract

A highly integrated dual conversion heterodyne GPS receiver is reported. The receiver chip includes a 2.9dB NF LNA, an image-reject mixer with 32dB image rejection. The on-chip IF chain, which consists of a VGA, a Znd mixer and filtering, has a maximum gain of 83dB, a gain range of 45dB and a 7dB NF. A 4-bit ADC is integrated on chip for enhanced SNR. The PLL with its VCO are also integrated. The total NF is 3dB with a total 121dB voltage gain. The chip consumes 132mW at 2. 7%'.

Methods and design techniques for the miniaturization of an L-band System-on-Package receiver front-end

“…Therefore, a quadrature downconverter must be used to avoid loss of information. The 90-degree phase shift can be created by means of a passive polyphase filter [62] or a hybrid coupler [63]. Process variations associated with the resistors and capacitors can severely reduce the performance of polyphase filters [62], while hybrid couplers may only be feasible at high frequencies where their size is reduced [63].…”