A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

Clark, Lawrence T.; Zhao, Daniel; Bakhishev, Teymur; Ahn, Hong Jo; Boling, Edward; Duane, Michael; Fujita, K.; Gregory, P. E.; Hoffmann, T.; Hori, M.; Kanai, D.; Kidd, David; Lee, S.; Liu, Y.; Mitani, J.; Nagayama, Jun; Pradhan, Sambhu Nath; Ranade, P.; Rogenmoser, R.; Scudder, L. R.; Shifren, L.; Torii, Y.; Wojko, M.; Asada, Y.; Ema, T.; Thompson, Scott E.

doi:10.1109/iedm.2012.6479042

Cited by 17 publications

(5 citation statements)

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“…The deeply depleted channel (DDC) MOS transistor has recently been announced by SuVolta as a competitor to FinFET and UTB-SOI MOS transistor, for its several advantages. These are reduced random dopant fluctuation (RDF) effect because of the use of lightly doped channel [2]- [3], increased carrier mobility due to reduced scattering of the carriers in the channel. In addition, as the DDC MOS transistor is based on the existing bulk CMOS technology with little modifications, the layout IPs of the bulk MOS transistors can be used for them.…”

Section: Introductionmentioning

confidence: 97%

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Threshold voltage modeling of Deeply Depleted Channel MOSFET and simulation study of its analog performances

Sengupta

Pandit

2014

International Conference on Electronics, Communication and Instrumentation (ICECI)

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This paper presents the analytical models for the long channel and short channel threshold voltage of Deeply Depleted Channel (DDC) MOS transistor. The model predicted results are compared with TCAD simulation results. This paper also reports the comparative study of the analog performances of the DDC MOS transistor with those of a uniformly doped transistor. The TCAD tool is calibrated with published data of DDC MOS transistor. The better immunity of the DDC MOS transistor in comparison to the conventional bulk MOS transistor is demonstrated through simulation results.

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Section: Introductionmentioning

confidence: 97%

“…In addition, as the DDC MOS transistor is based on the existing bulk CMOS technology with little modifications, the layout IPs of the bulk MOS transistors can be used for them. The DDC MOS transistor is implemented in 65nm process technology and reported in [3] - [6].…”

Section: Introductionmentioning

confidence: 99%

Threshold voltage modeling of Deeply Depleted Channel MOSFET and simulation study of its analog performances

Sengupta

Pandit

2014

International Conference on Electronics, Communication and Instrumentation (ICECI)

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“…We considered an external voltage source for the body biasing. However, similar biasing can be generated with minimal area overhead [37]. Recall that ULL DDC devices are optimized to reduce the leakage current while maintaining sufficient I ON .…”

Section: Resultsmentioning

confidence: 99%

“…The authors in [35] addressed the limitation of voltage scaling in bulk-CMOS by using extremely thin Silicon-On-Insulator SOI (ETSOI) for low-power applications. The ETSOI [35] and Tri-gate FET [36] structures with selectively grown epitaxial channels after shallow trench isolation (STI) improve performance but do not address V T variation due to RDF [37,38]. None of these technological advancements allow a 6T SRAM to operate in the subthreshold region or address subthreshold challenges stated in [2] and [24].…”

Section: Technology Considerationmentioning

confidence: 99%

Ultra-Low Power and Reliable SRAM for Systems-on-Chip

Patel¹

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The number of ubiquitous sensors has increased to more than double the human population and is expected to continue growing in the future. The pervasive use of sensors for applications such as personal healthcare and the Internet of Things (IoT) presents a growing sustainability challenge concerning the availability and accessibility of power sources. With 50 billion less BSN system. First, we explore different design knobs for an optimal SRAM design targeting ULP applications. These knobs include leveraging advanced fabrication technology, optimal device selection, circuit design techniques, and architectural techniques. Next, we evaluate the efficacy of different read and write peripheral assist techniques for improving reliability and energy efficiency of subthreshold SRAMs and provide stability, power, and performance trade-offs for system level optimization. The result of various optimization approaches resulted in a leakage and energy optimized SRAM operating over with leakage power reduced to 1.5 pW/bit while consuming only 6.24 pJ/access energy that is 40% more efficient than the previous version. To address a wide range of IoT applications with energy optimization, we propose a Canary sensor based minimum supply voltage (V M IN) tracking with optimal selection of the peripheral assist techniques. Later, we address the reliability issue at subthreshold operation using a process, voltage, and temperature (PVT) variation mitigation controller. Finally, the impact of the radiation-induced soft error is evaluated to provide a comprehensive study on reliability for the ULP SRAM at scaled V DD. Dedicating what all I learn in my life to 'Gurus' in my life-for enlightening my life with the knowledge, My Parents-for always giving me the courage to achieve impossible, My Wife-Pooja-for her unwavering love and motivation Meaning: Lead me from the unreal to the real; from darkness(ignorance) to light(knowledge); and from death to immortality. iv v Besides my life at the lab doing the research work, I immensely enjoyed my stay in Charlottesville. I am very much grateful to my neighbors for their pleasant company during my stay. I am also grateful to the members of Swadhyay Parivar for their selfless love. Last but never the least, I would like to thank my family members. I am very grateful for my parents, Naranbhai and Induben, for their continuous support and motivation for vii pursuing higher education. Especially, I thank my mother for always keeping me in her prayer while my father for giving me the courage to achieve whatever seems impossible to me. I thank my sister-Rinku-for her sisterly love. I cannot encompass my gratitude to my wife, Pooja, with the words for her support. She always been a lovely wife with continuous support. I am also indebted to almighty God for his blessing of two beautiful children, Samyak and Swara-my best stress busters! I cannot image myself completing my Ph.D. without the help of all these three-my wife and my kids-Thank you so much!

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“…Unlike dopant changes, an increase in the impurities makes RDF worse and increases junction leakage [78]. A DDC technology for 65nm [79][78] is designed to optimize the trade-off between V th variation and sub-threshold leakage. This paper describes new ULL devices in a 55nm DDC technology that target total leakage current reduction with RBB.…”

Section: Ddc Technologymentioning

confidence: 99%

Power Management in Ultra-Low Power Systems

Roy¹

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The evolving vision of the Internet-of-Things (IoT) will revolutionize various applications such as remote health monitoring, home automation and remote surveillance. It has been projected that by 2025, there will be 1 trillion IoT devices influencing our daily lives. This will result in the generation of an enormous amount of data, which will have to be stored, processed and transmitted efficiently and reliably. Although advancements in Integrated Circuit (IC) design and the availability of various Ultra-low Power (ULP) circuit components have helped us to visualize an ecosystem of numerous internet-connected devices, the overall system integration will become a major challenge. A System-on-Chip (SoC), catering to IoT applications is expected to contain many different circuit components such as sensors and Analog-Front-Ends (AFEs) for real-time signal acquisition, analog-to-digital converters, digital signal processors, memories, wireless transceivers etc. All these components have different supply voltage requirements and power profiles. Hence, power delivery to such components in an SoC will play an important role in the overall system architecture. Although, battery-powered systems have traditionally worked well in portable electronics but in an IoT ecosystem, the cost of battery replacement in a trillion-sensor node network will be enormous. In many applications, such as remote surveillance, systems require a long operational lifetime. Moreover, system deployment should be unobtrusive and hence such systems should have small form factors.The above requirements are hard to meet using conventional battery-powered systems. Hence, in most IoT SoCs, there is a strong motivation for an integrated Power Management Unit (PMU), with energy harvesting capability for near-perpetual battery-less operation, which i Abstract ii can provide a range of supply voltage rails to satisfy the electrical specifications of different functional units.This dissertation addresses the design challenges related to energy autonomy and powerdelivery in a wireless sensor node. This work presents an energy harvesting platform in context of a self-powered System-in-Package (SiP) with a capability to harvest from either photovoltaic or thermoelectric generators (TEGs). The SiP consists of an SoC for processing and storage, non-volatile memory, a wireless transceiver and various off-the-shelf sensors. To deliver power and to meet the electrical specifications of these different components of the sensor node, this work presents an efficient, low quiescent power, supply-voltage regulation scheme. In addition to power delivery, this dissertation also demonstrates several ULP digital and mixed-signal circuit components, commonly used in energy-autonomous and always-ON systems such as an event-driven wakeup receiver. This work describes circuit solutions and techniques related to power delivery that will enhance the operational lifetime, reduce the overall form-factor and contribute towards attaining energy-autonomy to facilitate a wide range of a...

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A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

Cited by 17 publications

References 0 publications

Threshold voltage modeling of Deeply Depleted Channel MOSFET and simulation study of its analog performances

Threshold voltage modeling of Deeply Depleted Channel MOSFET and simulation study of its analog performances

Ultra-Low Power and Reliable SRAM for Systems-on-Chip

Power Management in Ultra-Low Power Systems

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